Untitled
Abstract: No abstract text available
Text: 1.0 I n t r o d u c t io n 1.1.3 Circular Buffers The monolithic SUMMIT provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The SUMMIT is a single-chip device that implements all three of the defined MIL-STD-1553 functions Remote Terminal, Bus Controller, and Monitor. Operating
|
OCR Scan
|
MIL-STD-1553
maint553
139-pin
140-pin
V/-15
/-12V
|
PDF
|
Untitled
Abstract: No abstract text available
Text: e ^ Tstg Tj Vrm Io a s » -M Ä Ä £ ü $ 1SJ± 2, MWÆ mmm Ifsm 50Hz JESife 7 * ';> n s i i Ta=25t: 50Hz ÏL ^SM 3N £ * i£ L T i= 25t: Vf Ir B il 6 ja TL=25t: If=1A V r=V rm • V - KPbI • Ü H F b! ii y - -5 5 -1 5 0 150 600 0.75 1 45 V A V 1.1 10
|
OCR Scan
|
D1F60A
000505b
B2113Ã
0GG5027
|
PDF
|
SIS 661
Abstract: VM009 CA95C68 CA95C18 CA95C09 AM9518 AM9568 SDS S4 24V Z8000 nb11c
Text: NEWBRIDGE MICROSYSTEMS NEWBRIDGE MICROSYSTEMS =,4E D JANUARY 1993 • bSflfilOl DQOSQSS 35S ■ NBMC CA95C68/18/09 DES DATA CIPHERING PROCESSORS (DCP • Encrypts/Decrypts data using National Bureau of Standards Data Encryption Standard (DES) • High speed, pin and function compatible version
|
OCR Scan
|
CA95C68/18/09
AM9568,
AM9518
VM009
SIS 661
VM009
CA95C68
CA95C18
CA95C09
AM9568
SDS S4 24V
Z8000
nb11c
|
PDF
|
83C154D-16
Abstract: 83C154D-20
Text: Tem ic 83C154D MATRA MHS CMOS 0 to 30 MHz Single-Chip 8 Bit Microcontroller Description The MHS 83C154D retains all the features of the MHS 80C52 with extended ROM capacity 32 K bytes , 256 bytes of RAM, 32 I/O lines, a 6-source 2-level interrupts, a full duplex serial port, an on-chip oscillator and clock
|
OCR Scan
|
83C154D
83C154D
80C52
83C154D-16
83C154D-20
|
PDF
|
Untitled
Abstract: No abstract text available
Text: HY5216256 Series -HYUNDAI 256Kx 16-bit Video RAM with 2CAS Introduction Overview The 4megabit Video RAM is an application specific memory device designed for graphics applications. It comprises a 256k x16 DRAM memory array interfaced to a 256 x16 Serial Access Memory SAM , or register.
|
OCR Scan
|
HY5216256
256Kx
16-bit
16bits
4b750Ã
1VC01-00-MAY95
525mil
64pin
4b750flÃ
|
PDF
|
photodiode Responsivity
Abstract: PIN photodiode responsivity 1550nm 2,5 GHz FRM15w PIN Photodiode 1550nm 4 ghz
Text: • FHNH5W23WH D ES C R IP TIO N The FR M 15W 231C R is an APD pre-amplifier module for 1550nm wave length optical receiver front-end. It contains a planar InGaAs-APD Avalanche Phto-diode and a transimpedance type GaAs pre-amplifier IC. The InGaAs-APD, having high responsivity, low capacitance and low noise
|
OCR Scan
|
FHNH5W23WH
FRM15W231CR
1550nm
4T75b
0DD5057
FRM15W231CR
0005D5Ö
photodiode Responsivity
PIN photodiode responsivity 1550nm 2,5 GHz
FRM15w
PIN Photodiode 1550nm 4 ghz
|
PDF
|
IR 448H
Abstract: GR-1400 446H PDI 45A BPT T41 C02h ir 446h lm 741 using schmitt trigger PSL 26 PM5344
Text: PMC-Sierra, Inc. S TANDARD PRO DUCT PM C -951010 IS S U E 4 PM5362 TUPP-PLUS SONET/SDH TRIBUTARY U NIT PAYLOAD PROCESSOR FEA TU R ES • Configurable, multi-channel, payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial
|
OCR Scan
|
PMC-951010
28x28x3
49MMi
IR 448H
GR-1400
446H
PDI 45A
BPT T41
C02h
ir 446h
lm 741 using schmitt trigger
PSL 26
PM5344
|
PDF
|
CU01C
Abstract: 5962-8751410 AT28HC64-70 28HC64 A12C AT28HC64
Text: AT28HC64/L Features • • Fast Read Access Time - 55 ns Automatic Page Write Operation Internal Address and Data Latches for 32 Bytes Internal Control Timer • Fast Write Cycle Times Maximum Page Write Cycle Time: 2 ms 1 to 32 Byte Page W rite Operation
|
OCR Scan
|
AT28HC64/L
28HC64L)
Military/883C
107M177
CU01C
5962-8751410
AT28HC64-70
28HC64
A12C
AT28HC64
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GAL6001 Lattice High Performance E2CMOS FPLA Generic Array Logic Semiconductor • ■ ■ ■ Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 30ns Maxim um Propagation Delay — 27MHz Maxim um Frequency — 12ns Maxim um Clock to Output Delay
|
OCR Scan
|
GAL6001
27MHz
00050bb
|
PDF
|
NAIS 414
Abstract: 7 segment 5165
Text: NJU6423B 20-CHARACTER 2-LIN E DOT M A T R I X LCD CONTROLLER D R IV E R • GENERAL DESCRIPTION The NJUS423B is a 1 Chip Dot Matrix LCD controller driver for up to 20-character 2-1ine display. It contains voltage converter, bleeder resistance, CR oscillator, microprocessor interface circuits, instruc
|
OCR Scan
|
NJU6423B
20-CHARACTER
NJUS423B
NAIS 414
7 segment 5165
|
PDF
|
74LVX373
Abstract: 74LVX373M 74LVX373MTC 74LVX373MTCX 74LVX373MX 74LVX373SJ 74LVX373SJX
Text: LVX373 National Semiconductor 74LVX373 Low Voltage Octal Transparent Latch with TRI-STATE Outputs General Description Features The LVX373 consists of eight latches with TRI-STATE out puts for bus organized system applications. The latches ap pear transparent to the data when Latch Enable LE is
|
OCR Scan
|
74LVX373
LVX373
74lvx373
bS0115E
74LVX373M
74LVX373MTC
74LVX373MTCX
74LVX373MX
74LVX373SJ
74LVX373SJX
|
PDF
|
marking code 50Z
Abstract: smd marking code ADOR
Text: REVISIONS LTR DESCRIPTION DATE Redrawn with changes. Added device types 19 through 22. Added vendor CAGE 65786 for device types 19 and 20. Added vendor CAGE 61772 for devices 21 and 22. Corrected errors to Table I. Added pin 1 reference to case outline U.
|
OCR Scan
|
MIL-BUL-103
T00470Ã
marking code 50Z
smd marking code ADOR
|
PDF
|
R1C11
Abstract: r6c1
Text: Configuration selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing conventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from configuration data in serial form from a
|
OCR Scan
|
|
PDF
|