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Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04	PDF
Untitled Abstract: No abstract text available Text: 74AUP1G04 Low-power inverter Rev. 6 — 14 February 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04	PDF
Untitled Abstract: No abstract text available Text: 74AUP1G04 Low-power inverter Rev. 5 — 5 December 2011 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04	PDF
74AUP1G04 Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203 Text: 74AUP1G04 Low-power inverter Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall	Original	74AUP1G04 74AUP1G04 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW JESD22-A114-C MO-203	PDF
74AUP1G04 Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW 74AUP1G04GV Text: 74AUP1G04 Low-power inverter Rev. 03 — 5 November 2009 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW 74AUP1G04GV	PDF
74AUP1G04 Abstract: 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW Text: 74AUP1G04 Low-power inverter Rev. 4 — 30 June 2010 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04 74AUP1G04GF 74AUP1G04GM 74AUP1G04GW	PDF
001aaf022 Abstract: No abstract text available Text: 74AUP1G04 Low-power inverter Rev. 02.00 — 16 May 2006 Product data sheet 1. General description The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall	Original	74AUP1G04 74AUP1G04 001aaf022	PDF
Untitled Abstract: No abstract text available Text: 74AUP1G04 Low-power inverter Rev. 7 — 27 June 2012 Product data sheet 1. General description The 74AUP1G04 provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.	Original	74AUP1G04 74AUP1G04	PDF