Untitled
Abstract: No abstract text available
Text: 74HC237 3-to-8 line decoder, demultiplexer with address latches Rev. 6 — 23 August 2012 Product data sheet 1. General description The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL LSTTL . The 74HC237 is specified in compliance with JEDEC
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74HC237
74HC237
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74hc733
Abstract: 74HC73 74HC73N 74HC73D 74HC73DB 74HC73PW JESD22-A114E SSOP14 SSOP14 package
Text: 74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 04 — 19 March 2008 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. It is pin compatible with Low-power Schottky TTL LSTTL .
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74HC73
74HC73
74hc733
74HC73N
74HC73D
74HC73DB
74HC73PW
JESD22-A114E
SSOP14
SSOP14 package
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74AHC139
Abstract: 74AHCT139 74AHC139D 74AHC139PW HE4000B
Text: 74AHC139; 74AHCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 02 — 9 May 2008 Product data sheet 1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74AHC139;
74AHCT139
74AHCT139
AHCT139
74AHC139
74AHC139D
74AHC139PW
HE4000B
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AHCT32
Abstract: 74AHC32 74AHC32BQ 74AHC32D 74AHC32PW 74AHCT32 TSSOP14
Text: 74AHC32; 74AHCT32 Quad 2-input OR gate Rev. 04 — 22 May 2008 Product data sheet 1. General description The 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74AHC32;
74AHCT32
74AHCT32
74AHC32:
74AHCT32:
EIA/JESD22-A114E
EIA/JESD22-A115-A
AHCT32
74AHC32
74AHC32BQ
74AHC32D
74AHC32PW
TSSOP14
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2A5-10
Abstract: 74AHC02BQ 74AHC02 74AHC02D 74AHC02PW 74AHCT02 TSSOP14
Text: 74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 04 — 21 May 2008 Product data sheet 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74AHC02;
74AHCT02
74AHCT02
74AHC02:
74AHCT02:
EIA/JESD22-A114E
EIA/JESD22-A115-A
2A5-10
74AHC02BQ
74AHC02
74AHC02D
74AHC02PW
TSSOP14
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AHCT00
Abstract: 74AHC00D 74AHC00 74AHC00BQ 74AHC00PW 74AHCT00 TSSOP14
Text: 74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 04 — 28 April 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC
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74AHC00;
74AHCT00
74AHCT00
74AHC00:
74AHCT00:
EIA/JESD22-A114E
EIA/JESD22-A115-A
AHCT00
74AHC00D
74AHC00
74AHC00BQ
74AHC00PW
TSSOP14
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74HC164N PIN DIAGRAM
Abstract: 74hc164n 74HCT164 application note 74HC164 74HCT164 74HCT164BQ 74HC164D 74HC164DB 74HCT164D 74HCT164DB
Text: 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 5 — 25 November 2010 Product data sheet 1. General description The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL LSTTL . They are specified in compliance with JEDEC
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74HC164;
74HCT164
74HCT164
HCT164
74HC164N PIN DIAGRAM
74hc164n
74HCT164 application note
74HC164
74HCT164BQ
74HC164D
74HC164DB
74HCT164D
74HCT164DB
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Untitled
Abstract: No abstract text available
Text: 74HC175; 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger Rev. 3 — 31 March 2014 Product data sheet 1. General description The 74HC175; 74HCT175 are high-speed Si-gate CMOS devices which are pin compatible with Low-power Schottky TTL LSTTL .
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74HC175;
74HCT175
74HCT175
HCT175
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dhvqfn14
Abstract: 74AHC30 74AHC30D 74AHC30PW 74AHCT30 74AHCT30D 74AHCT30PW JESD22-A114E
Text: 74AHC30; 74AHCT30 8-input NAND gate Rev. 03 — 26 June 2009 Product data sheet 1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74AHC30;
74AHCT30
74AHCT30
74AHC30:
74AHCT30:
JESD22-A114E
JESD22-A115-A
dhvqfn14
74AHC30
74AHC30D
74AHC30PW
74AHCT30D
74AHCT30PW
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Untitled
Abstract: No abstract text available
Text: 74HC4002-Q100; 74HCT4002-Q100 Dual 4-input NOR gate Rev. 1 — 18 July 2012 Product data sheet 1. General description The 74HC4002-Q100; 74HCT4002-Q100 is a dual 4-input NOR gate. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to
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74HC4002-Q100;
74HCT4002-Q100
74HCT4002-Q100
AEC-Q100
74HC4002-Q100:
74HCT4002-Q1
HCT4002
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74HC157
Abstract: No abstract text available
Text: 74HC157; 74HCT157 Quad 2-input multiplexer Rev. 4 — 19 December 2011 Product data sheet 1. General description The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
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74HC157;
74HCT157
74HCT157
74HC/HCT157
74HC/HCT157.
HCT157
74HC157
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74HC30
Abstract: No abstract text available
Text: 74HC30; 74HCT30 8-input NAND gate Rev. 03 — 20 April 2010 Product data sheet 1. General description The 74HC30; 74HCT30 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .
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74HC30;
74HCT30
74HCT30
74HC30:
74HCT30:
JESD22-A114F
JESD22-A115-A
74HC30
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Untitled
Abstract: No abstract text available
Text: 74HC153-Q100; 74HCT153-Q100 Dual 4-input multiplexer Rev. 1 — 22 July 2013 Product data sheet 1. General description The 74HC153-Q100; 74HCT153-Q100 is a dual 4-input multiplexer. The device features independent enable inputs nE and common data select inputs (S0 and S1). For each
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74HC153-Q100;
74HCT153-Q100
74HCT153-Q100
HCT153
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74hc11
Abstract: No abstract text available
Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 5 — 16 December 2011 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .
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74HC11;
74HCT11
74HCT11
74HC11:
74HCT11:
JESD22-A114F
JESD22-A115-A
74hc11
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74HC215
Abstract: ttl 74hc21_3 74HC21 74HC21D 74HC21DB 74HC21N 74HC21PW JESD22-A114E SSOP14
Text: 74HC21 Dual 4-input AND gate Rev. 05 — 7 May 2009 Product data sheet 1. General description The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL LSTTL . The 74HC21 provide the 4-input AND function. 2. Features
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74HC21
74HC21
JESD22-A114E
JESD22-A115-A
74HC21N
DIP14
74HC215
ttl 74hc21_3
74HC21D
74HC21DB
74HC21N
74HC21PW
SSOP14
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Untitled
Abstract: No abstract text available
Text: 74HC04; 74HCT04 Hex inverter Rev. 4 — 3 August 2012 Product data sheet 1. General description The 74HC04; 74HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
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74HC04;
74HCT04
74HCT04
74HC04:
74HCT04:
JESD22-A114F
JESD22-A115-A
HCT04
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74hc164
Abstract: No abstract text available
Text: 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 6 — 12 December 2011 Product data sheet 1. General description The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL LSTTL . They are specified in compliance with JEDEC
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74HC164;
74HCT164
74HCT164
HCT164
74hc164
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Untitled
Abstract: No abstract text available
Text: 74AHC139; 74AHCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 02 — 9 May 2008 Product data sheet 1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74AHC139;
74AHCT139
74AHCT139
AHCT139
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hct14
Abstract: No abstract text available
Text: 74HC14; 74HCT14 Hex inverting Schmitt trigger Rev. 5 — 19 December 2011 Product data sheet 1. General description The 74HC14; 74HCT14 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with JEDEC standard
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74HC14;
74HCT14
74HCT14
EIA/JESD22-A114F
EIA/JESD22-A115-A
HCT14
hct14
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Untitled
Abstract: No abstract text available
Text: 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 6 — 14 December 2011 Product data sheet 1. General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .
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74HC00;
74HCT00
74HCT00
74HC00:
74HCT00:
JESD22-A114F
JESD22-A115-A
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Untitled
Abstract: No abstract text available
Text: 74HC74-Q100; 74HCT74-Q100 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 2 — 6 September 2013 Product data sheet 1. General description The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data nD , clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
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74HC74-Q100;
74HCT74-Q100
74HCT74-Q100
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Untitled
Abstract: No abstract text available
Text: 74HC151-Q100; 74HCT151-Q100 Quad 2-input multiplexer Rev. 1 — 7 August 2012 Product data sheet 1. General description The 74HC151-Q100; 74HCT151-Q100 are 8-bit multiplexer with eight binary inputs I0 to I7 , three select inputs (S0 to S2) and an enable input (E). One of the eight binary inputs is
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74HC151-Q100;
74HCT151-Q100
74HCT151-Q100
HCT151
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Untitled
Abstract: No abstract text available
Text: 74AHC30-Q100; 74AHCT30-Q100 8-input NAND gate Rev. 1 — 20 November 2013 Product data sheet 1. General description The 74AHC30-Q100; 74AHCT30-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL . It is specified in compliance with
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74AHC30-Q100;
74AHCT30-Q100
74AHCT30-Q100
AEC-Q100
AHCT30
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Untitled
Abstract: No abstract text available
Text: 74HC04-Q100; 74HCT04-Q100 Hex inverter Rev. 1 — 12 July 2012 Product data sheet 1. General description The 74HC04-Q100; 74HCT04-Q100 is a hex inverter. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of
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74HC04-Q100;
74HCT04-Q100
74HCT04-Q100
AEC-Q100
74HCns
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