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    Toshiba America Electronic Components TK100E10N1,S1X

    MOSFET N-CH 100V 100A TO220
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    DigiKey TK100E10N1,S1X Tube 2,816 1
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    Kyocera AVX Components 100E101GTN3600XJ24

    CAP CER 100PF 3.6KV P90 3838
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    DigiKey 100E101GTN3600XJ24 Bulk 41 1
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    ITT Interconnect Solutions CA3100E18-1S-B

    CONN RCPT W/SKT 10POS
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    DigiKey CA3100E18-1S-B Bulk 26 1
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    ITT Interconnect Solutions CA3100E10SL-3P-B-13

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    DigiKey CA3100E10SL-3P-B-13 Bag 26 1
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    ITT Interconnect Solutions CA3100E10SL-3P-B-03

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    DigiKey CA3100E10SL-3P-B-03 Bag 26 1
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    100E1 Datasheets (28)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    100E101GTN3600X Kyocera AVX Components Ceramic Capacitor 0.68UF 25V X5R 0603 Original PDF
    100E101JMN3600X American Technical Ceramics Capacitors - Ceramic Capacitors - CAP CER 100PF 3.6KV P90 3838 Original PDF
    100E101JT3600X American Technical Ceramics Capacitors - Ceramic Capacitors - CAP CER 100PF 3.6KV P90 3838 Original PDF
    100E101JT3600XJ24 American Technical Ceramics Ceramic Capacitor 100PF 3.6KV P90 3838 Original PDF
    100E1131-0.75-9/9/9-0 TE Connectivity Uncategorized - Miscellaneous - 100E1131-0.75-9/9/9-0 Original PDF
    100E1131-1.00-9/9/9-0 TE Connectivity Uncategorized - Miscellaneous - 100E1131-1.00-9/9/9-0 Original PDF
    100E1C15.5 Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 15.5KV Original PDF
    100E-1C-15.5 Littelfuse E Rated Medium Voltage Fuses Original PDF
    100E-1C-15.5 Littelfuse Medium Voltage Fuses - 2400 - 25,500 VAC, Current Limiting Original PDF
    100E1C15.5S Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 15.5KV SEA Original PDF
    100E1C2.75 Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 2.75KV Original PDF
    100E-1C-2.75 Littelfuse E Rated Medium Voltage Fuses Original PDF
    100E-1C-2.75 Littelfuse Medium Voltage Fuses - 2400 - 25,500 VAC, Current Limiting Original PDF
    100E1C5.5 Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 5.5KV Original PDF
    100E-1C-5.5 Littelfuse E Rated Medium Voltage Fuses Original PDF
    100E-1C-5.5 Littelfuse Medium Voltage Fuses - 2400 - 25,500 VAC, Current Limiting Original PDF
    100E1C8.25 Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 8.25KV Original PDF
    100E-1C-8.25 Littelfuse E Rated Medium Voltage Fuses Original PDF
    100E-1C-8.25 Littelfuse Medium Voltage Fuses - 2400 - 25,500 VAC, Current Limiting Original PDF
    100E1CL15.5 Littelfuse Electrical, Specialty Fuses, Circuit Protection, FUSE M/V E-RATED 100E 15.5KV BOL Original PDF

    100E1 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    E160

    Abstract: SY100E160 SY10E160 SY10E160JC
    Text: 12-BIT PARITY GENERATOR/CHECKER DESCRIPTION FEATURES • Provides odd-HIGH parity of 12 inputs ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes


    Original     		PDF 12-BIT SY10/100E160 SY10E160JC J28-1 SY10E160JCTR SY100E160JC SY100E160JCTR E160 SY100E160 SY10E160 SY10E160JC

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, 100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Text: MC10E104, 100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D marking CODE D2B MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, 100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    E160

    Abstract: E193 MC10193 SY100E193 SY10E193
    Text: Micrel, Inc. SY10E193 100E193 SY10E193 ERROR DETECTION/ CORRECTION CIRCUIT FEATURES 100E193 DESCRIPTION • Hamming code generation ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E193 are error detection and correction EDAC circuits designed for use in new, high- performance


    Original     		PDF SY10E193 SY100E193 SY10/100E193 MC10193. M9999-032006 E160 E193 MC10193 SY100E193 SY10E193

    MC100E171

    Abstract: MC10E171 MC10E171FN
    Text: MC10E171, 100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to


    Original     		PDF MC10E171, MC100E171 MC10E/100E171 MC10E171/D MC100E171 MC10E171 MC10E171FN

    MC100E151

    Abstract: MC10E151 MC10E151FN
    Text: MC10E151, 100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous


    Original     		PDF MC10E151, MC100E151 MC10E/100E151 MC10E151/D MC100E151 MC10E151 MC10E151FN

    MC100E150

    Abstract: MC10E150 MC10E150FN
    Text: MC10E150, 100E150 5V ECL 6-Bit D Latch Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the


    Original     		PDF MC10E150, MC100E150 MC10E/100E150 MC10E150/D MC100E150 MC10E150 MC10E150FN

    E112

    Abstract: E212 MC100E112 MC10E112 E212 transistor
    Text: MC10E112, 100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 MC10E112/D E112 E212 MC100E112 MC10E112 E212 transistor

    MC100E163

    Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
    Text: MC10E163, 100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.


    Original     		PDF MC10E163, MC100E163 MC10E/100E163 MC10E163FN EIA/JESD78 r14525 MC10E163/D MC100E163 MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2

    MC100E154

    Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
    Text: MC10E154, 100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on


    Original     		PDF MC10E154, MC100E154 MC10E/100E154 MC10E154FN r14525 MC10E154/D MC100E154 MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2

    E116

    Abstract: SK10E116PJ SK10E116PJT LM 380 FUNCTIONAL BLOCK AN-1002
    Text: SK10/100E116 Quint Differential Line Receiver HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100E116 is a quint differential line receiver designed for use in new, high-performance ECL systems. • • • • • • • • The receiver design features clamp circuitry to cause a


    Original     		PDF SK10/100E116 SK10/100E116 SK100E116PJ 28-PLCC SK100E116PJT AN1002 AN1003 AN1005 AN1006 E116 SK10E116PJ SK10E116PJT LM 380 FUNCTIONAL BLOCK AN-1002

    E166

    Abstract: SY100E166 SY10E166 SY10E166JC
    Text: 9-BIT MAGNITUDE COMPARATOR FEATURES SY10E166 100E166 DESCRIPTION • 1100ps max. Propagation Delay A = B ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E166 are 9-bit magnitude comparators designed for use in new, high-performance ECL systems.


    Original     		PDF SY10E166 SY100E166 1100ps SY10/100E166 MC10E/100E166 28-pin SY10E166JCTR J28-1 SY100E166JC E166 SY100E166 SY10E166 SY10E166JC

    MC100E157

    Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
    Text: MC10E157, 100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.


    Original     		PDF MC10E157, MC100E157 MC10E/100E157 MC10E157FN EIA/JESD78 r14525 MC10E158/D MC100E157 MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2

    pdc 140

    Abstract: DL140 E195 MC100E195 MC10E195
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.


    Original     		PDF MC10E195 MC100E195 MC10E/100E195 DL140 MC10E195/D* MC10E195/D pdc 140 E195 MC100E195 MC10E195

    motorola D-latch

    Abstract: MC100E150 DL140 MC10E150
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6ĆBit D Latch MC10E150 100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A


    Original     		PDF MC10E150 MC100E150 MC10E/100E150 800ps MC10E150/D* MC10E150/D DL140 motorola D-latch MC100E150 MC10E150

    DL140

    Abstract: E195 MC100E195 MC10E195
    Text: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.


    Original     		PDF MC10E195/D MC10E195 MC100E195 MC10E/100E195 DL140 E195 MC100E195 MC10E195

    Motorola, Inc. identical in pinout to

    Abstract: DL140 MC100E171 MC10E171
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 Multiplexer MC10E171 100E171 The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the


    Original     		PDF MC10E171 MC100E171 MC10E/100E171 725ps 28-Lead MC10E/D* MC10E/D DL140 Motorola, Inc. identical in pinout to MC100E171 MC10E171

    Untitled

    Abstract: No abstract text available
    Text: Order this document by MC10E136/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6-Bit U niversal Up/Down Counter M C 10E136 M C 100E136 • 550 MHz Count Frequency • • • • Fully Synchronous Up and Down Counting Internal 75 kQ Input Pulldown Resistors Look-Ahead-Carry Input and Output


    OCR Scan     		PDF MC10E136/D 10E136 100E136 MC10E/100E136

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M 100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition.


    OCR Scan     		PDF MC10E195 C100E195 MC10E/100E195 DL140

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6-Bit Universal Up/Down Counter M C10E136 M 100E136 The MC1OE/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading


    OCR Scan     		PDF C10E136 C100E136 MC1OE/100E136 24-bit DL140

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9 -B it S h ift R e g is te r M C 10E142 M C 100E142 The M C 10E/100E142 is a 9-bit shift register, designed with byte-parity a p p lic a tio n s in m ind. T h e E142 p e rfo rm s s e ria l/p a ra lle l in and serial/parallel out, shifting in one direction. The nine inputs DO - D8


    OCR Scan     		PDF 10E142 100E142 10E/100E142

    LC313

    Abstract: No abstract text available
    Text: MOTOROLA SEM ICONDUCTO R TECHNICAL DATA 6-Bit D Latch M C10E150 M 100E150 The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent and input data transitions propagate through to the output. A


    OCR Scan     		PDF C10E150 C100E150 MC10E/100E150 28-Lead LC313

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 10E 163 M C 100E163 • 850 p s M a x. D to O u tp u t • D iffe re n tia l O u tp u ts • E x te n d e d 100E V g g R ange o f - 4 . 2 V to - 5 . 4 6 V • 75 k i l In p u t P u lld o w n R esisto rs T h e M C 10E/100E163 c o n ta in s tw o 8:1 m u ltip le x e rs w ith d iffe re n tia l o u tp u ts a nd


    OCR Scan     		PDF 100E163 10E/100E163 28-LEAD