TMS320P14
Abstract: TMS320LC15
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320P14
TMS320LC15
|
PDF
|
TMS320P14
Abstract: TMS320LC15
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320P14
TMS320LC15
|
PDF
|
TMS320P14
Abstract: TMS320LC15 cy7c291 TMS320C1x TMS320C10 TMS320C10-14 TMS320C10-25 TMS320C14 TMS320C15 TMS320E14
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
TMS320C1x
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320P14
TMS320LC15
cy7c291
TMS320C10
TMS320C10-14
TMS320C10-25
TMS320C14
TMS320C15
TMS320E14
|
PDF
|
block diagram of TMS320C5X starter kit
Abstract: TMS320C5x architecture diagram fuzzy logic library pic c code TMS320C5x random noise generator XDS510 block diagram of of TMS320C4X architecture SEMINAR ON 4G TECHNOLOGY TMS320C1x TMS320C40 TMDS3080004
Text: Digital Signal Processing Selection Guide Revised 9/96 General DSP Literature TMS320 Digital Signal Processor Solutions Solutions for today Sockets to look for: 8-/16-/32-bit Microcontrollers General-purpose Microprocessors ● Competitor DSPs ● ● Advantages of designing
|
Original
|
TMS320
8-/16-/32-bit
TMS320C5x
TMS320C8x
TMS320C54x
TMS320C5x
16-Bit
block diagram of TMS320C5X starter kit
TMS320C5x architecture diagram
fuzzy logic library pic c code
TMS320C5x random noise generator
XDS510
block diagram of of TMS320C4X architecture
SEMINAR ON 4G TECHNOLOGY
TMS320C1x
TMS320C40
TMDS3080004
|
PDF
|
MIP 4110
Abstract: SEMINAR ON 4G TECHNOLOGY SPRT125 TMDS3200026 block diagram of TMS320C5X starter kit SPRA019 SPRU076 MCU320-EXPLORE architecture of TMS320C53 bga 8X16
Text: General DSP Literature TMS320 Digital Signal Processor Solutions Solutions for today Sockets to look for: ● ● ● 8-/16-bit Microcontrollers General-purpose Microprocessors Competitor DSPs Advantages of designing with DSPs over other Microprocessors: ●
|
Original
|
TMS320
8-/16-bit
/mirrors/tms320bbs'
MIP 4110
SEMINAR ON 4G TECHNOLOGY
SPRT125
TMDS3200026
block diagram of TMS320C5X starter kit
SPRA019
SPRU076
MCU320-EXPLORE
architecture of TMS320C53
bga 8X16
|
PDF
|
TMS320LC15
Abstract: TMS320P14 TMS320C16
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320LC15
TMS320P14
TMS320C16
|
PDF
|
UPD482445
Abstract: upd482444 UPD482445G5-60 upd482445g5 UPD482445GW-70 UPD482445GW uPD482444GW-70
Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT Description The µPD482444 and µPD482445 have a random access port and a serial access port. The random access port has a 4M-bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock
|
Original
|
PD482444,
256K-WORD
16-BIT
PD482444
PD482445
UPD482445
upd482444
UPD482445G5-60
upd482445g5
UPD482445GW-70
UPD482445GW
uPD482444GW-70
|
PDF
|
sub-micro CMOS technology
Abstract: No abstract text available
Text: VG26 V S4260D 262,144 x 16 - Bit CMOS Dynamic RAM VIS Description The device is CMOS Dynamic RAM organized as 262, 144-word x 16 bits. It is fabricated with an advanced submicro CMOS technology and advanced CMOS circuit design technologies. Fast Page Mode allows 512 random
|
Original
|
S4260D
144-word
16-bit
40pin,
400mil
VG26S4260D)
VG26VS4260D)
sub-micro CMOS technology
|
PDF
|
TMS320LC15
Abstract: TMS320C16 TMS320P14
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
TMS320C1x
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320LC15
TMS320C16
TMS320P14
|
PDF
|
VG26426
Abstract: No abstract text available
Text: VG264260CJ 262,144 x 16 - Bit CMOS Dynamic RAM VIS Description The device is CMOS Dynamic RAM organized as 262, 144-word x 16 bits. It is fabricated with an advanced submicron CMOS technology and advanced CMOS circuit design technologies. It is packaged in
|
Original
|
40-pin
VG264260CJ
144-word
25/28/30/35/40ns
1G5-0109
VG26426
|
PDF
|
TMS320P14
Abstract: TMS320LC15
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
TMS320C1x
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320P14
TMS320LC15
|
PDF
|
TMS320LC15
Abstract: LC-15 C16S TMS320P14
Text: TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM
|
Original
|
TMS320C1x
SPRS009C
144/256-Word
TMS320E14/P14/E15/P15/E17/P17)
TMS320P14/P15/P17)
64K-Word
32-Bit
16-Bit
TMS320LC15
LC-15
C16S
TMS320P14
|
PDF
|
TC524258
Abstract: TC524259BJ C69 WML dsf03
Text: TOSHIBA TC524259B s il ic o n g a t e c m o s 262, 144WORDS X 4BITS MULTIPORT DRAM target DESCRIPTION The TC524259B is a CMOS multiport memory equipped with a 262,144-words by 4-bits dynamic random access memory RAM port and a 512-words by 4-bits static serial access memory (SAM) port. The TC524259B
|
OCR Scan
|
144WORDS
TC524259B
TC524259B
144-words
512-words
TC524258B
C-112
TC524258
TC524259BJ
C69 WML
dsf03
|
PDF
|
tc524256
Abstract: EM 5103 miele ram 5101 TOSHIBA cmos memory -NAND TC524256AJ 512x4bit TC524256AJ/AZ-12 TC524256AZ
Text: TOSHIBA DIGITAL INTEGRATED CIRCUIT INTEGRATED CIRCUIT TOSHIBA TC524256AJ / AZ -10 , TC524256AJ/AZ-12 TECHNICAL DATA SILIC O N G A T E C M O S P R E L IM IN A R Y 262, 144WORDS X4BITS MULTIPORT DRAM DESCRIPTION The TC 524256A J/A Z is a CMOS m ultiport memory equipped with a 262,144-words by 4-bits
|
OCR Scan
|
TC524256AJ
TC524256AJ/AZ-12
144WORDS
TC524256AJ/AZ
144-words
512-words
28Pin
400mil
tc524256
EM 5103
miele
ram 5101
TOSHIBA cmos memory -NAND
512x4bit
TC524256AZ
|
PDF
|
|
|
TRW J500
Abstract: k45752 52S marking
Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ / /¿PD42S4260L, 424260L 3.3 V OPERATION 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The fiPD42S4260L, 424260L are 262 144 words by 16 bits dynamic CMOS RAMs. The fast page mode and
|
OCR Scan
|
uPD42S4260L
uPD424260L
16-BIT,
fiPD42S4260L,
424260L
PD42S4260L
44-pin
40-pin
/jPD42S4260L-A70,
424260L-A70
TRW J500
k45752
52S marking
|
PDF
|
TMS44C256
Abstract: TMS44C256-10 TMS44C256-80 44C256
Text: TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY ‘jM G S l'M C D Q1 I u 1 DQ4 W ; 3 18 ' D Q 3 V SS DQ2 I 7 RAS ! 9 R E AD 13 j A 6 12 j A5 TIM E T IM E TIM E OR ta R ta (C ) 'a (C A ) W R IT E A3 [ 9 (tC A A ) CYCLE (M A X ) (M A X ) (M IN)
|
OCR Scan
|
TMS44C256
144-WORD
TMS44C256s
TMS44C256N
TMS44C256-10
TMS44C256-80
44C256
|
PDF
|
Untitled
Abstract: No abstract text available
Text: V Ì T S ’J B ’S ’- " M 5 '_ S ’ :5 M 4 4 2 5 6 B P , J , L , V P , R V - 7 L , - f i L , - 1.0 1 . FAST PAGE MODE 104857G-BIT 262144-W 0RD BY 4-BIT DYNAMIC RAM DESCRIPTION This is a family of 262144-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process, and
|
OCR Scan
|
104857G-BIT
62144-W
262144-word
442S6BP,
04SS76-BIT
2S2144-WORD
44256BP,
1048576-BIT
262144-m
44256BP
|
PDF
|
25608
Abstract: M5M5256 MH25608TNA-10H
Text: MITSUBISHI LSIs MH25608TNA-85L,-10L,-12L,-15L/ MH25608TNA-85H,-10H,-12H,-15H 2 0 9 7 1 5 2 -B IT 2 6 2 144-WORD BY 8-BIT CM 0S STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M H 2 5 6 0 8 T N A is a 2 0 9 7 1 5 2 bits CMOS static R A M module organized as 26 2144 -w o rd s by 8-bits. It consists
|
OCR Scan
|
MH25608TNA-85L
MH25608TNA-85H
144-WORD
32-pin
100ns
120ns
150ns
25608
M5M5256
MH25608TNA-10H
|
PDF
|
D015
Abstract: MSC2328B-10YS2 MSC2328B-60YS2 MSC2328B-70YS2 MSC2328B-80YS2
Text: O K I Semiconductor MSC2328B-XXYS2 262,144-Word by 8-Bit DRAM Module: Fast Page Mode DESCRIPTION The OKI M SC2328B-xxYS2 is a fully decoded 262/144-word x 8-bit CM OS Dynamic Random Access M em ory Module composed of two 1-Mb DRAMs in SOJ M SM514256B packages mounted with two 0.2 |iF
|
OCR Scan
|
MSC2328B-xxYS2
144-Word
MSC2328B-xxYS2
MSM514256B)
30-pin
60thin
D015
MSC2328B-10YS2
MSC2328B-60YS2
MSC2328B-70YS2
MSC2328B-80YS2
|
PDF
|
Untitled
Abstract: No abstract text available
Text: bM27S25 004203b ^70 A T A SHEET EC MOS INTEGRATED CIRCUIT /¿PD42S4190, 424190 4 M-BIT DYNAMIC RAM 256K-WORD BY 18-BIT, FAST PAGE MODE, BYTE WRITE MODE DESCRIPTION The //PD42S4190, 424190 are 262 144 w ords by 18 bits dynamic CMOS RAMs. The fast page m ode and byte
|
OCR Scan
|
bM27S25
004203b
PD42S4190,
256K-WORD
18-BIT,
//PD42S4190,
PD42S4190
44-pin
40-pin
|
PDF
|
UPD482445GW-70
Abstract: UPD482445
Text: DATA SHEET MOS INTEGRATED CIRCUIT UPD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT D es crip tio n The ,uPD482444 and ,uPD482445 have a random access port and a serial access port. The random access port has a 4M-bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock
|
OCR Scan
|
uPD482444
uPD482445
256K-WORD
16-BIT
UPD482445GW-70
|
PDF
|
42S421
Abstract: I2758 uPD424210-60-G eZ 752 SCZ7 NEC Japan 424210-60 7PP4
Text: PRELIMINARY DATA SH EET_ / M O S IN T E G R A T E D CIRCUIT ¿/PD42S4210-60-G,424210-60-G 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The ¿/PD42S4210-60-G,424210-60-G is 262 144 words by 16 bits dynamic CM OS RAMs with optional
|
OCR Scan
|
uPD42S4210-60-G
uPD424210-60-G
16-BIT,
pPD42S4210-60-G
424210-60-G
44-pin
40-pin
/PD42S4210-60-G
42S421
I2758
eZ 752
SCZ7
NEC Japan 424210-60
7PP4
|
PDF
|
UPD482445
Abstract: PD482444
Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / /;PD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT D e s c rip tio n The ¿¿PD482444 and //PD482445 have a random access port and a serial access port. The random access port has a 4M -bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock
|
OCR Scan
|
uPD482444
uPD482445
256K-WORD
16-BIT
PD482444
//PD482445
/xPD482445
03it8
/PD482444,
jiPD482444,
|
PDF
|
LH6C4265
Abstract: LH6C4265AK-40
Text: SHARP SPEC No. I SSUE: EL08Z014 DEC. 17 1996 To : S P E C I F Product Type_ 4M I C A T I O N S D R A M 2561 x 16bit _ L H 6 C 4 2 6 5 A K —40 M odel No. (LH6C4H4K) SKThis specifications contains 28 pages including the cover and appendix.
|
OCR Scan
|
EL08Z014
16bit)
SOJ40-M0O
AA1I44
LH6C4265
LH6C4265AK-40
|
PDF
|