ITR17
Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
Text: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or
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29C94
29C94
ITR17
ITR24
80X86
AD10
AD11
AD12
AD14
ITR28
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29C94
Abstract: ANM036 line E1 e1-t1
Text: ANM036 MATRA MHS Connecting 29C96 and 29C94 Introduction The 29C94 and 29C96 are parts of MHS's ISDN primary rate chipset. The 29C94 is a multichannel HDLC controller and the 29C96 is a framer with time slots switching capabilities. These two components can be used in T1-DS1 1.544MHz or E1-CEPT
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ANM036
29C96
29C94
29C94
544MHz)
048MHz)
29C3xx
ANM036
line E1
e1-t1
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AD10
Abstract: AD11 AD12 AD14 AD17
Text: 29C948 MATRA MHS 8 Channel HDLC/V.120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear
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29C948
29C948
AD10
AD11
AD12
AD14
AD17
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One-chip telephone IC
Abstract: telephone line voice amplifier Voice to e1 converter circuit U 4076 One-chip telephone cordless IC VN2410* mosfet BFP67 slc96 remote terminal E1 PCM encoder V30 CPU
Text: TEMIC Semiconductors Communication Segment Digital Networks Wireless Communication Wired Communication Communication We’ve been supporting advances in communications industry for decades. Today, we continue to offer the best combination of applications knowledge and leading-edge solutions required by the
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29C93A
102/V
V25bis)
PQFP44
29C93A
29C921
80C51
One-chip telephone IC
telephone line voice amplifier
Voice to e1 converter circuit
U 4076
One-chip telephone cordless IC
VN2410* mosfet
BFP67
slc96 remote terminal
E1 PCM encoder
V30 CPU
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mxt 211
Abstract: signalling and frame alignment in E1 G704 SLC96 alarm frame format b30 c300 - 1 tsr1-24
Text: 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or E1-CEPT transceivers. The 29C96 supports following frame formats : D DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)
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29C96
29C96
SLC-96
29C94
mxt 211
signalling and frame alignment in E1
G704
SLC96 alarm frame format
b30 c300 - 1
tsr1-24
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BCR131
Abstract: 448H IT28 PCM255
Text: 29C98 MATRA MHS B-Channel Resynchronizer Description ISDN public networks CENTRAL OFFICES usually implement channel switching except on leased lines. When higher data rates than 64 kbps are required between two terminals or between a terminal and a server or host machine, and normal ISDN connection
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29C98
29C98
BCR131
448H
IT28
PCM255
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JFET TRANSISTOR REPLACEMENT GUIDE j201
Abstract: UA6538 DC motor speed control using 555 and ir sensor U2740B-FP UAA145 CQY80 U2840B tcrt9050 TCDF1910 sod80 smd zener diode color band
Text: Semiconductors Technical Library March 1996 Back Products Overview Communications Automotive Computer Industrial Broadcast Media Aerospace & Defense Communications Applications Telephone ICs Type U3750BM–CP Package 44–pin PLCC Function One chip telephone
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U3750BM
U3760MB-FN
U3760MB-SD
SSO-44
SD-40
U3800BM
U3810BM
U4030B
U4030B
JFET TRANSISTOR REPLACEMENT GUIDE j201
UA6538
DC motor speed control using 555 and ir sensor
U2740B-FP
UAA145
CQY80
U2840B
tcrt9050
TCDF1910
sod80 smd zener diode color band
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5962L0053605VYC
Abstract: 5962-9069204QXA ATMEL 302 24C16 UT9Q512E-20YCC MOH0268D UT54ACS164245SEIUCCR Z085810 5962-9762101Q2A UT28F256QLET-45UCC 5962R0250401KXA
Text: NOT MEASUREMENT SENSITIVE MIL-HDBK-103AJ 19 SEPTEMBER 2011 SUPERSEDING MIL-HDBK-103AH 28 MARCH 2011 DEPARTMENT OF DEFENSE HANDBOOK LIST OF STANDARD MICROCIRCUIT DRAWINGS This handbook is for guidance only. Do not cite this document as a requirement. AMSC N/A
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MIL-HDBK-103AJ
MIL-HDBK-103AH
MIL-HDBK-103AJ
5962L0053605VYC
5962-9069204QXA
ATMEL 302 24C16
UT9Q512E-20YCC
MOH0268D
UT54ACS164245SEIUCCR
Z085810
5962-9762101Q2A
UT28F256QLET-45UCC
5962R0250401KXA
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DM 311 BG 40
Abstract: DM 311 BG 42 K/DM 311 BG 29 DM 311 BG 30
Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description T he MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of high speed data links based on
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29C94
29C94
29C3XX
29C96,
DM 311 BG 40
DM 311 BG 42
K/DM 311 BG 29
DM 311 BG 30
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ITR30
Abstract: 0804H
Text: Tem ic 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on
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29C94
MHS29C94
29C3XX
29C96,
29C94
ITR30
0804H
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ITR30
Abstract: 29C948 ITR24
Text: Tem ic 29C948 MATRA MHS 8 Channel HDLC/V. 120 Protocol Controller Introduction The 29C948 is an 8 channel data link protocol controller circuit. It multiplexes/demultiplexes up to 8 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or clear
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29C948
29C948
ITR30
ITR24
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ir transmitter receiver
Abstract: IRDA module UART Si9961CY transceiver rs232 driver receiver
Text: Tem ic S e m i c o n d u c t o r s SO 16 ^ S024 Mass Storage ICs : PärtNüBiber Function Key Features Package Source Disk-Drive/ Optical Drive ICs SÌ9961CY VCM driver • Cost-effective solution • No dead band • Zero cross over distortion S024 SC Interface ICs
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9961CY
U2532B-FP
OIM3000
OIM3232
I15kHz)
PQFP44
PLCC68
ir transmitter receiver
IRDA module UART
Si9961CY
transceiver rs232 driver receiver
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EIT30
Abstract: 29C93
Text: T e m ic 29C98 MATRA MHS B-Channel Resynchronizer Description ISDN public networks CENTRAL OFFICES usually implement channel switching except on leased lines. When higher data rates than 64 kbps are required between two terminals or between a terminal and a
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29C98
29C98
QDD474b
D0D4747
EIT30
29C93
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tsr1-24
Abstract: mxt 211 RSR1-24 B18 IC marking code EL B17
Text: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formater Description T he 29C96 is a program m able CM OS device interfacing with T1 DS1 or E l (CEPT) transceivers. T he 29C96 supports following fram e form ats : • DS1 : 4 fram es (D M I), D4 (G704), ESF (G704),
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29C96
29C96
SLC-96
tsr1-24
mxt 211
RSR1-24
B18 IC marking code
EL B17
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mxt 211
Abstract: No abstract text available
Text: Tem ic 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or El-CEPT transceivers. The 29C96 supports following frame formats : • DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)
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29C96
29C96
SLC-96
00470t.
mxt 211
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MQFPF256
Abstract: LCC68
Text: Tem ic S e m i c o n d u c t o r s PLCC28 S 028 On-Board Computers Part Number Function Key Features Package Source TSC691E 32-bit SPARC computer: integer unit Radiant tolerant, 10 Mips @ 14 MHz, JTAG interface MQFPF256 NT TSC692E 32-bit SPARC computer: floating-point unit
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PLCC28
TSC691E
32-bit
MQFPF256
TSC692E
MQFPF160
TSC693E
656XX
LCC68
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Untitled
Abstract: No abstract text available
Text: Tem ic 29C95 MATRA MHS Multi-Channel ECMA 102/VI 10 Protocol Controller Description T he M HS 29C95 is a m ulti-channel data link protocol controlller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support im plem entation of data links based on either the
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29C95
102/VI
29C95
29C3XX
29C96
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Untitled
Abstract: No abstract text available
Text: PREVIEW H IM mWWmSM SEPTEMBER 1988 DATA 29C94 MULTI CHANNEL HDLC CONTROLLER _ MAIN FEATURES_ • TARGETTED FOR ISON PRIMARYACCESS 23B+D OR 30B+D HDLC LAYER 2 PROCESSING • SUPPORTS UPTO 31 64 Kb/s FULL DUPLEX
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29C94
29C94
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29C843A
Abstract: 29c843
Text: REVISIONS DATE YR-MO-DA DESCRIPTION LTR Add PRESET and CLEAR propagation delays to table I for device types 02 and 04. Change figure 4. Editorial changes throughout. 88/07/22 Added devices 05 and 06. Changes to table I, Editorial changes throughout. 92/11/02
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MIL-BUL-103.
MIL-BUL-103
29C843A
29c843
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