Untitled
Abstract: No abstract text available
Text: fax id: 3550 CY7B991V 3.3V RoboClock „.¿ s a - CYPRESS Low Voltage Programmable Skew Clock Buffer functions. These multiple-output dock drivers provide the sys tem integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual driv
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80-MHz
32-pin
CY7B991V
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WEW4
Abstract: CY7B991 CY7B992 QS5991 QS5992 QS5993 q529
Text: Q u a l it y S e m ic o n d u c t o r , I n c . QS5991 QS5992 QS5993 PRELIMINARY Programmable Skew PLL Clock Driver TurboClock FEATURES/BENEFITS DESCRIPTION • • • The QS599X family is a high fanout PLL based clock driver intended for high performance computing and
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QS5991
QS5992
QS5993
200ps
250ps
75MHz
100MHz
QS599X
QS5991:
QS5992:
WEW4
CY7B991
CY7B992
q529
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1.SKE 350
Abstract: No abstract text available
Text: Programmable Skew PLL Clock Driver S e m ic o n d u c t o r , In c. QS5991 QS5992 QS5993 TurboClock" p r e lim in a r y FEATURES/BENEFITS DESCRIPTION • • • The QS599X family is a high fanout PLL based clock driver intended for high performance computing and
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QS5991
QS5992
QS5993
200ps
250ps
75MHz
100MHz
QS599X
QS5991:
QS5992:
1.SKE 350
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Untitled
Abstract: No abstract text available
Text: Q u a lity Sem iconductor, Inc. 3.3V Programmable Skew qssv993 PLL Clock Driver m p r e l im in a r y T u r b O u lO C k FEATURES/BENEFITS DESCRIPTION • The QS5V99X family is a high fanout 3.3V PLL based clock driver intended for high performance computing
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qssv993
QS5V99X
S5V991:
32-pin
QS5V993:
28-pin
200ps
250ps
75MHz
85MHz
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diagram mid 1002
Abstract: CY7B991V CY7B991V-2JC CY7B991V-5JC CY7B991V-7JC pin diagram for mid 1002
Text: rr-rrrrrrroit"^. CY7B991V 3.3V RoboClock . W CYPRESS: Low Voltage Programmable Skew Clock Buffer Features functions. These multiple-output clock drivers provide the sys tem integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual driv
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CY7B991V
80-MHz
32-pin
CY7B991V
diagram mid 1002
CY7B991V-2JC
CY7B991V-5JC
CY7B991V-7JC
pin diagram for mid 1002
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diagram mid 1002
Abstract: CY7B9911
Text: fax id: 3547 CY7B9911 RoboClock+ High Speed Programmable Skew Clock Buffer PSCB Features tions. T his m ultiple -ou tp ut clo ck drive r pro vid es the system in te g ra to r w ith fun ctions necessary to optim ize the tim ing of h igh -perform a nce com p uter system s. Eight individual T TL
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CY7B9911
75-to
100-MHz
32-pin
diagram mid 1002
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CY7B991V
Abstract: R2130
Text: fax id: 3550 CY7B991V 3.3V RoboClock W OYPHESS Low Voltage Programmable Skew Clock Buffer PRELIMINARY Features functions. T hese m ultiple-output clo ck drivers provide the sys tem integrator w ith fun ctions ne cessa ry to optim ize the tim ing o f h igh -perform a nce co m p u te r system s. Eight individual d riv
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CY7B991V
80-MHz
32-pin
R2130
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Untitled
Abstract: No abstract text available
Text: CYPRESS SEMICONDUCTOR b5E T> 2 5 0 ^ 2 QQ1Q7T2 CYP CY7B991 CY7B992 PRELIMINARY CYPRESS SEMICONDUCTOR TÔ2 P rogram m ab le Skew C lock B u ffer P S C B Functional Description • Output pair skew <100 ps typical (250 max.) • All outputs skew <250 ps typical
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CY7B991
CY7B992
T-90-20
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CY7B991V
Abstract: CY7B991V-2JC CY7B991V-5JC pin diagram for mid 1002
Text: CY7B991V 3.3V RoboClock Low Voltage Programmable Skew Clock Buffer Features • All output pair skew <100 ps typical 250 max. • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted
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CY7B991V
80-MHz
32-pin
CY7B991V
CY7B991V-2JC
CY7B991V-5JC
pin diagram for mid 1002
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Untitled
Abstract: No abstract text available
Text: CY7B991V 3.3V RoboClock Low Voltage Programmable Skew Clock Buffer Features • All output pair skew <100 ps typical 250 max. • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted
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CY7B991V
80-MHz
32-pin
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CY7B991
Abstract: No abstract text available
Text: CY7B991 CY7B992 -ÿ C Y PR E SS Features • All output pair skew < 100 ps typical 250 max. • 3.75- to 80-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted — Operation at Vi and lA input
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CY7B991
CY7B992
80-MHz
32-pin
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Untitled
Abstract: No abstract text available
Text: / U 9 3 A . I I I C .V I & I PEP * P IQS.' Revision: Tuesday, February 9,1993 CY7B991 CY7B992 PRELIMINARY CYPRESS • . SEMICONDUCTOR Programmable Skew Clock Buffer PSCB Features Functional Description • O utput p air skew <100 ps typical (250 max.) • All outputs skew <250 ps typical
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CY7B991
CY7B992
80-MHz
75MHz)
32-pin
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