C1995
Abstract: DM74S473 DM74S473J DM74S473N DM74S473V J20A 512 ttl prom 9715
Text: DM74S473 512 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 8 bits configuration A memory enable input is provided to control the output states When the device is enabled the outputs represent the contents of the selected
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DM74S473
4096-Bit
C1995
DM74S473
DM74S473J
DM74S473N
DM74S473V
J20A
512 ttl prom
9715
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CY7C225A
Abstract: No abstract text available
Text: 1CY 7C22 5A CY7C225A 512 x 8 Registered PROM Features • TTL-compatible I/O • Direct replacement for bipolar PROMs • CMOS for optimum speed/power • Capable of withstanding greater than 2001V static • High speed discharge — 18 ns address set-up Functional Description
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CY7C225A
CY7C225A
300-mil
28-pin
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d 92-02
Abstract: AM27S25 DM77SR476 DM87SR476N J24A D 9202 N24A
Text: DM77SR476/DM87SR476 CTl National Æà Semiconductor DM77/87SR476 512 x 8 4k-Bit Registered TTL PROM General Description The DM 77/87SR476 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chip. This device is organized as 512 words by
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DM77/87SR476
DM77/87SR476
d 92-02
AM27S25
DM77SR476
DM87SR476N
J24A
D 9202
N24A
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DM74S475N
Abstract: DM74S475V J24A V28A
Text: DM54S475/DM74S475 Egl National æA Semiconductor DM54/74S475 512 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 8 bits configuration. Memory enable inputs are provided to control the output states. W hen the device is
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DM54/74S475
4096-Bit
DM74S475N
DM74S475V
J24A
V28A
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74S474
Abstract: DM74S474N DM74S474 DM54S474J DM54S474BJ DM74S474AN J24A N24A 74S474J DM54S474
Text: DM54S474/DM74S474 ZgA National Mm Semiconductor DM54/74S474 512 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 8 bits configuration. Memory enable inputs are provided to control the output states. W hen the device is
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DM54/74S474
4096-Bit
74S474
DM74S474N
DM74S474
DM54S474J
DM54S474BJ
DM74S474AN
J24A
N24A
74S474J
DM54S474
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74S472
Abstract: 74S472 PROM PROGRAMMING dm74s472 DM74S472N 91911 J20A DM74S472AN 472an DM74S472AJ
Text: DM54S472/DM74S472 National SjM Semiconductor DM54/74S472 512 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 8 bits configuration. A memory enable input is pro vided to control the output states. When the device is en
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DM54/74S472
4096-Bit
74S472
74S472 PROM PROGRAMMING
dm74s472
DM74S472N
91911
J20A
DM74S472AN
472an
DM74S472AJ
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74S473
Abstract: DM74S473AJ DM74S473AN DM74S473N DM74S473V J20A V20A 74s* programming
Text: DM54S473/DM74S473 yw\National fZA Semiconductor DM54S473/DM74S473 512 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 w ords by 8 bits configuration. A memory enable input is pro vided to control the output states. When the device is en
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DM54S473/DM74S473
4096-Bit
74S473
DM74S473AJ
DM74S473AN
DM74S473N
DM74S473V
J20A
V20A
74s* programming
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DM77
Abstract: DM87SR27N DM87SR27BJ DM87SR27BN J22A N22A
Text: DM77SR27/DM87SR27 VWA National éH à Sem iconductor DM77/87SR27 512x8 4k-Bit Registered TTL PROM General Description The DM77/87SR27 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chip. This device is organized as 512 words by
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DM77/87SR27
DM77/87SR27
DM77
DM87SR27N
DM87SR27BJ
DM87SR27BN
J22A
N22A
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DM77
Abstract: DM77SR181 DM87SR474BJ DM87SR474J DM87SR474N J24A N24A 474BJ
Text: DM77SR474/DM87SR474 National à jà Semiconductor DM77/87SR474 5 12x 8 4k-Bit Registered TTL PROM General Description The DM77/87SR474 is an electrically programmable Schottky TTL read-only memory with D-type, master-slave registers on-chip. This device is organized as 512 words by
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DM77/87SR474
DM77/87SR474
DM77
DM77SR181
DM87SR474BJ
DM87SR474J
DM87SR474N
J24A
N24A
474BJ
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Untitled
Abstract: No abstract text available
Text: CMOS EEPROM KM93C57/KM93C67 2K/4K Bit Serial Electrically Erasable PROM FEATURES GENERAL DESCRIPTION • Single 5 volt supply • Low power consumption — Active: 3 mA TTL — Standby: 250/JV (TTL) • User selectable memory organization — 256 x 16 o r 512 x 8 for KM93C67
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KM93C57/KM93C67
250/JV
KM93C67
KM93C57
KM93C57/67
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DM74S571
Abstract: DM74S571N DM74S571V J16A N16A programming TiW PROMs DM74S571J
Text: DM74S571 S3 National ÆÆ Semiconductor DM74S571 512 x 4 2048-Bit TTL PROM General Description Features This S chottky m em ory is organized in the popular 512 w ords by 4 bits configuration. A m em ory enable input is pro vided to control th e output states. W hen the device is en
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DM74S571
2048-Bit
DM74S571
DM74S571N
DM74S571V
J16A
N16A
programming TiW PROMs
DM74S571J
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY KM93C57/KM93C67 CMOS EEPROM 2K /4 K Bit Serial Electrically Erasable PROM FEATURES GENERAL DESCRIPTION • Single 5 volt supply • Low power consumption — Active: 3 mA TTL — Standby: 100 A (TTL) • User selectable memory organization — 256 x 16 or 512 x 8 for KM93C67
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KM93C57/KM93C67
KM93C67
KM93C57
KM93C57/67
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microprogram
Abstract: N3002 jump 74S182 N3001
Text: Signetics N3001 Microprogram Control Unit Product Specification Logic Products PIN CONFIGURATION FEATURES DESCRIPTION • Schottky TTL process • 45ns cycle time typ. • Direct addressing of standard bipolar PROM or ROM • 512 microinstruction addressability
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N3001
N3001
N3002,
74S182,
microprogram
N3002
jump
74S182
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MB7116E
Abstract: MB7116-W mb7116 MB7116E-W fujitsu 1988 MB711 MB710 fujitsu prom
Text: June 1990 Edition 3.0 FUJITSU DATA SHEET MB7116E-W/7116L-W PROGRAMMABLE SCHOTTKY2048-BIT READ ONLY MEMORY SCHOTTKY 2048-BIT DEAP PROM 512 WORDS x 4 BITS The Fujitsu M B7116-W is high speed Schottky TTL electrically field programm able read only memory organized as 512 words by 4 bits. With three-state outputs on the MB7116-W, memory
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MB7116E-W/7116L-W
SCHOTTKY2048-BIT
2048-BIT
B7116-W
MB7116-W,
MB7116E
MB7116-W
mb7116
MB7116E-W
fujitsu 1988
MB711
MB710
fujitsu prom
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microprogram
Abstract: microprogram control unit 74S182 N3001 N3002
Text: Sìgnetics N3001 Microprogram Control Unit Product Specification Logic Products PIN CONFIGURATION FEATURES DESCRIPTION • Schottky TTL process • 45ns cycle time <typ. • Direct addressing of standard bipolar PROM or ROM • 512 microinstruction addressability
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N3001
N3001
N3002,
74S182,
N30CM
microprogram
microprogram control unit
74S182
N3002
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82S131
Abstract: GDFP2-F16 GDIP1-T16 82S130A 82S131A
Text: Product specification Philips Semiconductors Military Bipolar Memory Products 2K-bit TTL bipolar PROM 512 x 4 82S131A DESCRIPTION FEATURES The 82S130A and 82S131A are field-programmable, which means that custom patterns are immediately available by following the
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82S130A
82S131A
-150pA
82S130A:
82S131A:
270ft
82S131
GDFP2-F16
GDIP1-T16
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82S141/8708+prom
Abstract: No abstract text available
Text: Philips Semiconductors Military Bipolar Memory Products Product specification 4K-bit TTL bipolar PROM 512 x 8 82S141 FEATURES • Microprogramming • Address access time: 90ns max • Hardwired algorithms • Input loading: -150jiA max • Control store
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82S141
-150jiA
82S141
1002b
711002b
82S141/8708+prom
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AS-016
Abstract: 82S147 82S147A f0035 AS016 33-OS
Text: Product specification Philips Semiconductors Military Bipolar Memory Products 4K-bit TTL bipolar PROM 512 x 8 82SH7A FEATURES DESCRIPTION • Address access time: 75ns max The 82S147 and 82S147A are field-programmable, which means that custom patterns are immediately available by following the
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82S147
82S147A
w82S147A
500ns
AS-016
f0035
AS016
33-OS
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DM74S474
Abstract: 74S474 74S474 programming DM54S474/DM74S474 74S474+programming -74S474
Text: DM54S474/DM74S474 \ National Semiconductor DM54/74S474 5 1 2 x 8 4096-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 8 bits configuration. Memory enable inputs are provided to control the output states. When the device is
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DM54S474/DM74S474
DM54/74S474
4096-Bit
DM74S474
74S474
74S474 programming
DM54S474/DM74S474
74S474+programming
-74S474
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AM27S25
Abstract: DM77 DM77SR476 SR25V SR25B
Text: DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B National Semiconductor Corporation DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B 512 x 8 4k-Bit Registered TTL PROM G eneral Description The D M 77 /8 7 S R 47 6 is an e lectrically program m able
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DM77/87SR476,
DM77/87SR25,
DM77/87SR476B,
DM77/87SR25B
DM77/87SR476
AM27S25
DM77
DM77SR476
SR25V
SR25B
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DM74S570AJ
Abstract: 74s570 DM74S570N DM74S570V J16A N16A DM74S570
Text: DM54S570/DM74S570 National Semiconductor DM54/74S570 5 1 2x4 2048-Bit TTL PROM General Description Features This Schottky memory is organized in the popular 512 words by 4 bits configuration. A memory enable input is pro vided to control the output states. When the device is en
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DM54/74S570
2048-Bit
DM74S570AJ
74s570
DM74S570N
DM74S570V
J16A
N16A
DM74S570
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X 1077 CE
Abstract: No abstract text available
Text: P hilips Sem iconductors M ilitary B ipo la r Memory P roducts P roduct sp ecifica tio n 4K-bit TTL bipolar PROM 512 x 8 82S141 FEATURES • Microprogramming • Address access time: 90ns max • Hardwired algorithms • Input loading: -150|iA max • Control store
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82S141
82S141
X 1077 CE
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82s141
Abstract: GDFP2-F24 82S141/BJA 1000U 82S141 philips ue-12
Text: P hilips Sem iconductors M ilitary B ipo la r Memory P roducts P roduct sp ecifica tio n 4K-bit TTL bipolar PROM 512 x 8 82S141 FEATURES • Microprogramming • Address access time: 90ns max • Hardwired algorithms • Input loading: -150|iA max • Control store
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82S141
24-pin
600mil-wide)
82S141/BJA
GDIP1-T24
82S141/BKA
GDFP2-F24
1000U.
82s141
GDFP2-F24
1000U
82S141 philips
ue-12
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82s141
Abstract: 512 ttl prom 1000U GDIP1-T24 82S141 philips 82S141/BJA
Text: P hilips Sem iconductors M ilitary B ipo la r Memory P roducts P roduct sp ecifica tio n 4K-bit TTL bipolar PROM 512 x 8 82S141 FEATURES • Microprogramming • Address access time: 90ns max • Hardwired algorithms • Input loading: -150|iA max • Control store
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82S141
24-pin
600mil-wide)
82S141/BJA
GDIP1-T24
82S141/BKA
GDFP2-F24
1000U.
82s141
512 ttl prom
1000U
GDIP1-T24
82S141 philips
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