Untitled
Abstract: No abstract text available
Text: Issue 5.0 November 1999 Description Block Diagram Available in PGA PUMA 2 and Gullwing (PUMA77) footprints. The PUMA *F16006 is a 16MBit FLASH module user configurable as 512K x 32, 1M x 16 or 2M x 8. The device is available with access times of 70, 90
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2/77F16006/A
PUMA77)
F16006
16MBit
120ns.
MIL-STD-883.
77F16006
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Untitled
Abstract: No abstract text available
Text: Issue 5.0 November 1999 Description Block Diagram Available in PGA PUMA 2 and Gullwing (PUMA77) footprints. The PUMA *F16006 is a 16MBit FLASH module user configurable as 512K x 32, 1M x 16 or 2M x 8. The device is available with access times of 70, 90
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PUMA77)
F16006
16MBit
120ns.
MIL-STD-883.
77F16006
2F16006AMB
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Untitled
Abstract: No abstract text available
Text: Issue 5.1 May 2001 Description Block Diagram Available in PGA PUMA 2 and Gullwing (PUMA77) footprints. The PUMA *F16006 is a 16MBit FLASH module user configurable as 512K x 32, 1M x 16 or 2M x 8. The device is available with access times of 70, 90 and 120ns.
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PUMA77)
F16006
16MBit
120ns.
MIL-STD-883.
77F16006
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Untitled
Abstract: No abstract text available
Text: Issue 5.1 May 2001 Description Block Diagram Available in PGA PUMA 2 and Gullwing (PUMA77) footprints. The PUMA *F16006 is a 16MBit FLASH module user configurable as 512K x 32, 1M x 16 or 2M x 8. The device is available with access times of 70, 90 and 120ns.
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PDF
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PUMA77)
F16006
16MBit
120ns.
MIL-STD-883.
77F16006
880/456/2May
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Untitled
Abstract: No abstract text available
Text: Issue 5.1 May 2001 Description Block Diagram Available in PGA PUMA 2 and Gullwing (PUMA77) footprints. The PUMA *F16006 is a 16MBit FLASH module user configurable as 512K x 32, 1M x 16 or 2M x 8. The device is available with access times of 70, 90 and 120ns.
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2/77F16006/A/B
PUMA77)
F16006
16MBit
120ns.
MIL-STD-883.
77F16006
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Untitled
Abstract: No abstract text available
Text: Issue 5.1 May 2001 Description The PUMA2SF4006 is a mixed technology ceramic PGA module organised as 128K x 16 SRAM and 128K x 16 FLASH. The PUMA2 has a industry standard footprint, the device can be user configured as 8 or 16 bit wide. High speed 5V FLASH and SRAM technology is
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2SF4006
PUMA2SF4006
120ns
MIL-STD-883C
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Untitled
Abstract: No abstract text available
Text: Issue 5.1 May 2001 Description The PUMA2SF4006 is a mixed technology ceramic PGA module organised as 128K x 16 SRAM and 128K x 16 FLASH. The PUMA2 has a industry standard footprint, the device can be user configured as 8 or 16 bit wide. High speed 5V FLASH and SRAM technology is
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2SF4006
PUMA2SF4006
120ns
MIL-STD-883C
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HARRIS 7555
Abstract: 7555 harris "Humidity Sensor" 7555 timer LMC555 TLC555 TS555 HTS2010 TLC555 humidity HPC008
Text: TECHNICAL 1 DATA TEMPERATURE AND RELATIVE HUMIDITY SENSOR HTS2010SMD Based on a unique capacitive cell for humidity measurement and a Negative Temperature Coefficient NTC thermistor for temperature measurement, this dual purpose relative humidity / temperature miniaturized sensor is designed for high volume, cost sensitive applications with tight space
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HTS2010SMD
HTS2010n
HPC008
HARRIS 7555
7555 harris
"Humidity Sensor"
7555 timer
LMC555
TLC555
TS555
HTS2010
TLC555 humidity
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HTS2010
Abstract: HARRIS 7555 7555 harris HPC008 HPP804B101 "Humidity Sensor" dew point sensor NTC Thermistor 10000 Ohm LMC555 HTS2010SMD
Text: TECHNICAL 1 DATA TEMPERATURE AND RELATIVE HUMIDITY SENSOR HTS2010SMD Based on a unique capacitive cell for humidity measurement and a Negative Temperature Coefficient NTC thermistor for temperature measurement, this dual purpose relative humidity / temperature miniaturized sensor is designed for high volume, cost sensitive applications with tight space
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HTS2010SMD
HPC008
HTS2010
HARRIS 7555
7555 harris
HPP804B101
"Humidity Sensor"
dew point sensor
NTC Thermistor 10000 Ohm
LMC555
HTS2010SMD
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xtr655
Abstract: temper sensor
Text: XTRM Series XTR650 HIGH-TEMPERATURE VERSATILE TIMER FEATURES DESCRIPTION ▲ Supply voltage from 2.8V to 5.5V. ▲ Operational beyond the -60°C to +230°C temperature range. ▲ Monostable, Astable, PWM and PPM modes of operation. ▲ Complementary, non-overlapping outputs.
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XTR650
XTR655:
200pF
XTR650
DS-00100-11
xtr655
temper sensor
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Tyco amp v.35 connectors
Abstract: v.35 connector connector iso 2593 114-10004 Application Specification 21393 213300-2 AMP catalog 82003 BB 555 iso 2593 LR7189
Text: Data downloaded from http://www.anglia.com - the website of Anglia - tel: 01945 474747 M Series Pin and Socket Connectors Catalogue 1654741 Revised 1-04 Special Application Connectors 9 Pin and Socket Connectors V.35 Connector The 34 position V.35 Connector is fully assembled
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MC100LVEP14
Abstract: TSSOP-20 MC100LVEP14DTG 0201 footprint
Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or
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MC100LVEP14
MC100LVEP14
LVEP14
MC100LVEP14/D
TSSOP-20
MC100LVEP14DTG
0201 footprint
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1775 data sheet
Abstract: TSSOP20 FOOTPRINT MC100LVEP14 TSSOP-20
Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or
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MC100LVEP14
MC100LVEP14
LVEP14
MC100LVEP14/D
1775 data sheet
TSSOP20 FOOTPRINT
TSSOP-20
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Untitled
Abstract: No abstract text available
Text: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With
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MC100LVEP05
MC100LVEP05
MC100EP05
LVEL05
KVP05
MC100LVEP05/D
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Untitled
Abstract: No abstract text available
Text: W29GL128C 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: August 2, 2013 Revision H BLANK W29GL128C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL128C
128M-BIT
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29gl128
Abstract: 11x13mm
Text: W29GL128C 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: May 31, 2011 Preliminary - Revision D BLANK W29GL128C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL128C
128M-BIT
29gl128
11x13mm
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W29GL128
Abstract: No abstract text available
Text: W29GL128C 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: October 18, 2011 Preliminary - Revision E BLANK W29GL128C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL128C
128M-BIT
W29GL128
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W29GL128CH9T
Abstract: W29GL128CL9b W29GL 29gl128 W29GL128C W29GL128 TSOP56 FOOTPRINT marking 6ah 56-PIN LFBGA64
Text: W29GL128C 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: August 31, 2010 Preliminary - Revision B BLANK W29GL128C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL128C
128M-BIT
W29GL128CH9T
W29GL128CL9b
W29GL
29gl128
W29GL128C
W29GL128
TSOP56 FOOTPRINT
marking 6ah
56-PIN
LFBGA64
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W29GL064C
Abstract: w29gl064 land pattern for TSOP 56 pin 48-pin TFBGA Footprint
Text: W29GL064C 64M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: May 31, 2011 Preliminary - Revision D BLANK W29GL064C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL064C
64M-BIT
W29GL064C
w29gl064
land pattern for TSOP 56 pin
48-pin TFBGA Footprint
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KVP05
Abstract: ku05 26 MC100 MC100EP05 MC100LVEP05 KU05 MC100LVEP05DTG
Text: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With
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MC100LVEP05
MC100LVEP05
MC100EP05
LVEL05
KVP05
MC100LVEP05/D
KVP05
ku05 26
MC100
MC100EP05
KU05
MC100LVEP05DTG
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datasheet of ic 555
Abstract: IC 555 DATA Sheet IC 555 PIN CONFIGURATION IC 555 datasheet ic 555 555 ic 865 IC marking application note ic 555 data sheet book ic 555 KVP11
Text: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for
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MC10LVEP11,
MC100LVEP11
MC10/100LVEP11
LVEP11
MC10LVEP11/D
datasheet of ic 555
IC 555
DATA Sheet IC 555
PIN CONFIGURATION IC 555
datasheet ic 555
555 ic
865 IC marking
application note ic 555
data sheet book ic 555
KVP11
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Untitled
Abstract: No abstract text available
Text: W29GL128C 128M-BIT 3.0-VOLT PARALLEL FLASH MEMORY WITH PAGE MODE Publication Release Date: January 19, 2011 Preliminary - Revision C BLANK W29GL128C Table of Contents 1 2 3 4 5 6 7 GENERAL DESCRIPTION . 1
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W29GL128C
128M-BIT
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MC100LVEP14
Abstract: No abstract text available
Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or
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MC100LVEP14
MC100LVEP14
LVEP14
MC100LVEP14/D
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1E83
Abstract: fast 555
Text: 5 = = — = T= IB M 11D8 3 6 0 B IB M 1 1E83 6 0 B P relim in ary 8M x 36 D R A M M odule Features • 72-Pin JEDEC Standard Single-ln-Line Memory Module • Performance: 1rac RAS Access Time 'CAC CAS Access Time •m Access Time From Address >RC Cycle Time
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OCR Scan
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PDF
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72-Pin
110ns
130ns
IBM11D8360B
IBM11E8360B
8360BA)
03H7151
MMDS27DSU-00
1E83
fast 555
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