adum3223
Abstract: adum4223 ADP3624 ADP3654 24-Lead LFCSP footprint
Text: Digital Controller for Isolated Power Supply with PMBus Interface ADP1051 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Versatile, digital voltage mode controller High speed, input voltage feed-forward control 6 PWM logic outputs with 625ps resolution
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ADP1051
ADP1051
ADP1051ACPZ-RL
ADP1051ACPZ-R7
ADP1051-240-EVALZ
ADP1051DC1-EVALZ
24-Lead
adum3223
adum4223
ADP3624
ADP3654
24-Lead LFCSP footprint
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smd 100uf Cha
Abstract: 5304 smd 8 pin ISPPAC-CLK5308S-01TN48I MBR120VLSFT1G RC0805JR-0710KL 100uF CHA ECS-3953M ic 5304 smd 8 pin SMD 100 6n cap DS1010
Text: ispClock Family Handbook HB1006 Version 01.4, November 2009 ispClock Family Handbook Table of Contents November 2009 Handbook HB1006 Section I. ispClock Family Data Sheets ispClock5600A Family Data Sheet. 1-1
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HB1006
HB1006
ispClock5600A
ispClock5400D
ispClock5300S
AN6080
smd 100uf Cha
5304 smd 8 pin
ISPPAC-CLK5308S-01TN48I
MBR120VLSFT1G
RC0805JR-0710KL
100uF CHA
ECS-3953M
ic 5304 smd 8 pin
SMD 100 6n cap
DS1010
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NS208N
Abstract: ns208
Text: Frequently Asked Questions about the RoboClockII Family The following questions are frequently asked by customers who are using devices in the RoboClock family. The RoboClockII family consists of the CY7B993V and CY7B994V. The following are brief answers to sometimes complicated questions. More
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CY7B993V
CY7B994V.
NS208N
ns208
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Micron Designline Vol 8
Abstract: DDR SDRAM designline DQSQ Micron NAND DQS dram ddr 1997 PC266 Micron DDR SDRAM designline 368-3945 ddr designline 1999 ddr designline 1998
Text: ○ SDR ○ DDR ○ /2N ○ PC100/ SDRAM DRAM ○ ○ 2 SDRAM CK 1 ○ ○ ○ SDR Single Data Rate ○ ○ ○ DDR Double Data Rate SDRAM DDR SDRAM ○ ○ ○ PC133 ○ DDR SDRAM ○ ○ ○ DRAM SDR SDR ○ 2 2 2) DDR SDRAM ○ 3 WRITE DDR 2N ○ READ
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PC100/
PC133
256-Mb
Micron Designline Vol 8
DDR SDRAM designline
DQSQ
Micron NAND DQS
dram ddr 1997
PC266
Micron DDR SDRAM designline
368-3945
ddr designline 1999
ddr designline 1998
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5V995
Abstract: IDT5V995
Text: IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II IDT5V995 ADVANCED INFORMATION FEATURES: DESCRIPTION • • • • The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
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IDT5V995
IDT5V995
5V995
5V995
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SMPTE 1080p level a
Abstract: No abstract text available
Text: 0XOWL GEN GF9330 High Performance SDTV/HDTV Deinterlacer PRELIMINARY DATA SHEET DEVICE OVERVIEW • De-interlace, Pass-Through and Film Frame Rate Down Conversion modes of operation The GF9330 is a high performance VDSP engine that performs high quality de-interlacing of interlaced digital
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GF9330
10-bit
12-bit
C-101,
SMPTE 1080p level a
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Managing High-Speed Clocks in High-Performance Satellite Systems
Abstract: Clock Management all component symbols backplane design cpci TDS7704B cpci backplane schematic P43-44 UT7R995
Text: Aeroflex Colorado Springs Page 1 Managing High-Speed Clocks in High-Performance Satellite Systems By Tim Meade, Standard Products Manager, Aeroflex Colorado Springs A s spaceborn applications continue to demand increased bandwidth and performance in their electronic subsystems, the need to manage high-speed
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UT7R995
Managing High-Speed Clocks in High-Performance Satellite Systems
Clock Management
all component symbols
backplane design cpci
TDS7704B
cpci backplane schematic
P43-44
UT7R995
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718G
Abstract: 5V9950 IDT5V9950
Text: IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. IDT5V9950 PRELIMINARY FEATURES: DESCRIPTION: • • • • The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
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IDT5V9950
IDT5V9950
5V9950
718G
5V9950
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CY7B9945V
Abstract: CY7B9945V-2AXC CY7B9945V-2AXCT CY7B9945V-2AXIT CY7B9945V-5AXC CY7B9945V-5AXCT HWT 09 322f
Text: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB window ■ 24 MHz –200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL Outputs driving 50Ω terminated lines
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CY7B9945V
CY7B9945V
625ps/1300
CY7B9945V-2AXC
CY7B9945V-2AXCT
CY7B9945V-2AXIT
CY7B9945V-5AXC
CY7B9945V-5AXCT
HWT 09
322f
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ALI chipset
Abstract: KM266 SIS 650 Via KM266 48MHZ M1671 PLL202-151 ali m1671 KM26
Text: PRELIMINARY PLL202-151 Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM FEATURES • • • • • • • • • • • • • Supports VIA P4M/KM266, ALI M1671 and SIS 645/650 Chipsets. Programmable Spread Spectrum Modulation from ±0.1% to ±1.5% with minim u m step size of
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PLL202-151
P4M/KM266,
M1671
ALI chipset
KM266
SIS 650
Via KM266
48MHZ
PLL202-151
ali m1671
KM26
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Untitled
Abstract: No abstract text available
Text: IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. IDT5V9950 ADVANCED INFORMATION FEATURES: DESCRIPTION: • • • • The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
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IDT5V9950
185ps
250ps
200MHz
100ps
32-pin
5V9950
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Untitled
Abstract: No abstract text available
Text: IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE IDT5V996 PRELIMINARY 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM II PLUS FEATURES: DESCRIPTION: • • • • The IDT5V996 is a high fanout PLL based clock driver intended for high
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IDT5V996
150ps
350ps
25MHz
225MHz
144-pin
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5V995
Abstract: AN237 IDT5V995
Text: IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II IDT5V995 FEATURES: DESCRIPTION: • • • • The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
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IDT5V995
IDT5V995
5V995
5V995
AN237
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Untitled
Abstract: No abstract text available
Text: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB window ■ 24 MHz –200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL outputs driving 50Ω terminated lines
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CY7B9945V
CY7B9945V
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hc322
Abstract: EP3C5 EP4SE230 HC371 LVDS_RX EP3SE50 EP4SE530 HC210 receiver LVDS_rx EP2AGX190
Text: Quartus II Software Device Support Release Notes RN-01045-1.0 May 2009 This document provides late-breaking information about device support in this version of the Altera Quartus® II software. For information about disk space and system requirements, refer to the readme.txt file in your altera/<version number>/quartus directory.
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RN-01045-1
hc322
EP3C5
EP4SE230
HC371
LVDS_RX
EP3SE50
EP4SE530
HC210
receiver LVDS_rx
EP2AGX190
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EP2AGX190
Abstract: EP3CLS200 EP2AGX125 EP4SE230 EP4SE530 EP2AGX260 HC210 EP2AGX45 EP3CLS150 EP3CLS70
Text: Quartus II Software Device Support Release Notes RN-01047-1.0 June 2009 This document provides late-breaking information about device support in this version of the Altera Quartus® II software. For information about disk space and system requirements, refer to the readme.txt file in your altera/<version number>/quartus directory.
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RN-01047-1
EP2AGX190
EP3CLS200
EP2AGX125
EP4SE230
EP4SE530
EP2AGX260
HC210
EP2AGX45
EP3CLS150
EP3CLS70
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2DS1
Abstract: CY7B993V CY7B994V 24185
Text: RoboClockII CY7B994V ADVANCED INFORMATION CY7B993V High-Speed Multi-Phase PLL Clock Buffer Features • Matched pair outputs skew <200 ps 200 ps MAX • 3.3V BiCMOS Technology • 12−100 MHz (CY7B993V), or 24−185 MHz (CY7B994V) output operation • 18 3.3V LVTTL outputs
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CY7B994V
CY7B993V
CY7B993V)
CY7B994V)
625ps
2DS1
CY7B993V
CY7B994V
24185
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5V9950
Abstract: IDT5V9950
Text: IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. IDT5V9950 ADVANCED INFORMATION FEATURES: DESCRIPTION: • • • • The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
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IDT5V9950
IDT5V9950
5V9950
5V9950
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CHL8318
Abstract: ASP1212
Text: Digital Multi-Phase Buck Controller FEATURES DESCRIPTION • Intel VR11.x compliant Digital PWM Controller Programmable 1-phase to 8-phase operation Customized Digital Over-Clocking features an easy-to-use SMBus Gamer command and a Gamer VID control up to 2.3V, Gamer Vmax,
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ASP1212
56-Pin
CHL8318
ASP1212
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Untitled
Abstract: No abstract text available
Text: IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. FEATURES: • • • • DESCRIPTION: Ref input is 5V tolerant 4 pairs of programmable skew outputs
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IDT5V9950
185ps
250ps
200MHz
100ps
5V9950
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5V995
Abstract: IDT5V995
Text: IDT5V995 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II IDT5V995 PRELIMINARY FEATURES: DESCRIPTION • • • • The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
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IDT5V995
IDT5V995
5V995
5V995
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GF9330
Abstract: GF9330-CBP GF9331 GS9021 ieee format for w16 engine SMPTE 296M smpte 274m image enhancer
Text: 0XOWL GEN GF9330 High Performance SDTV/HDTV Deinterlacer PRELIMINARY DATA SHEET DEVICE OVERVIEW • De-interlace, Pass-Through and Film Frame Rate Down Conversion modes of operation The GF9330 is a high performance VDSP engine that performs high quality de-interlacing of interlaced digital
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GF9330
GF9330
10-bit
C-101,
GF9330-CBP
GF9331
GS9021
ieee format for w16 engine
SMPTE 296M
smpte 274m
image enhancer
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5V9950
Abstract: IDT5V9950
Text: IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. IDT5V9950 FEATURES: DESCRIPTION: • • • • The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
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IDT5V9950
IDT5V9950
5V9950
5V9950
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B2F1
Abstract: 5V9955 AN237 IDT5V9955 ML51
Text: IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W IDT5V9955 FEATURES: DESCRIPTION • • • • The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended
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IDT5V9955
IDT5V9955
5V9955
B2F1
5V9955
AN237
ML51
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