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Catalog Datasheet	MFG & Type	PDF	Document Tags
c2xxx Abstract: PL611-20 marking code sot-23 697 marking code sot23 697 Text: PL611-20 Programmable Quick Turn Clock T M FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 PL611-20 • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical	Original	PDF	PL611-20 200MHz 10MHz-30MHz 75MHz c2xxx PL611-20 marking code sot-23 697 marking code sot23 697
Untitled Abstract: No abstract text available Text: PL611-01 Programmable Clock T M FEATURES •  XIN,FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN, FIN 3 PL611-01    Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical	Original	PDF	PL611-01 30-70ps 200MHz 10MHz-30MHz 75MHz 200MHz
Untitled Abstract: No abstract text available Text: Cavity Filters ◆ Features - Combline K&L Microwave’s series of combline filters covers the frequency range from 500MHz to 40000MHz. These filters are available with 2 to 17 resonant sections, and bandwidths from 3% to 20%. Although standard designs offer	Original	PDF	500MHz 40000MHz. 7FV20-6000/T600-O/O
PL611-30 Abstract: P611-30 Text: Preliminary Programmable Quick Turn Clock T M FEATURES PIN CONFIGURATION • Advanced programmable PLL design  Very low Jitter and Phase Noise < 40ps Pk-Pk typ.  Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs.  Output Frequencies:	Original	PDF	400MHz 10MHz 30MHz 75MHz 200MHz PL611-30 P611-30
PL611-31 Abstract: p611 31-XXX Text: Programmable Quick Turn Clock T M FEATURES •          PIN CONFIGURATION Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Up to 3 outputs Output frequency up to 200MHz CMOS. o Provides complementary LVCMOS outputs to	Original	PDF	200MHz 10MHz 30MHz 200MHz PL611-31 p611 31-XXX
PL611-30 Abstract: No abstract text available Text: Preliminary PL611-30 Programmable Quick Turn Clock T M PIN CONFIGURATION FEATURES • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL,	Original	PDF	PL611-30 375MHz 10MHz-30MHz 75MHz 200MHz PL611-30
ABPX1101-XXXSC Abstract: ABPX1101-XXXMC ABPX1101-XXXSC-T abracon programming 3digit up down counter A1XXX Text: ABPX1101 Advanced Programmable Clock FEATURES • • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK0 1 GND 2 XIN/FIN 3 ABPX1101 • • Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical	Original	PDF	ABPX1101 30-70ps 200MHz 10MHz-30MHz 75MHz 200MHz ABPX1101-XXXSC ABPX1101-XXXMC ABPX1101-XXXSC-T abracon programming 3digit up down counter A1XXX
ABPX1130-XXXSC Abstract: ABPX1130-XXXMC ABPX1130-XXXSC-T APBX1130-XXX abracon programming Text: Preliminary ABPX1130 Advanced Programmable Clock FEATURES • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL, LVDS XIN/FIN	Original	PDF	ABPX1130 375MHz 10MHz-30MHz 75MHz 200MHz ABPX1130-XXXSC ABPX1130-XXXMC ABPX1130-XXXSC-T APBX1130-XXX abracon programming
Untitled Abstract: No abstract text available Text: ABPX1120 Advanced Programmable Clock FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 ABPX1120 • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical	Original	PDF	ABPX1120 200MHz 10MHz-30MHz 75MHz
PL611-01 Abstract: PL611-01-XXXMC PL611-01-XXXSC dd marking Text: Programmable Quick Turn Clock T M FEATURES •          PIN CONFIGURATION Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical Up to 3 programmable outputs Output frequency up to 200MHz CMOS. Accepts Crystal or reference clock inputs	Original	PDF	30-70ps 200MHz 10MHz-30MHz 75MHz 200MHz PL611-01 PL611-01-XXXMC PL611-01-XXXSC dd marking
XTAL 50MHZ Abstract: PL611-25 RS-30 24V Text: PL611-25 Programmable Quick Turn Clock T M FEATURES PAD LAYOUT AND DIE ID • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise < 40ps Pk-Pk typical Two registers banks for 2-time programming. Output frequency up to 200MHz CMOS.	Original	PDF	PL611-25 200MHz 10MHz-30MHz 75MHz C611A- 0505-05D XTAL 50MHZ PL611-25 RS-30 24V
PL611-01 Abstract: marking code PDB PL611-01-XXXMC PL611-01-XXXSC Text: PL611-01 Programmable Quick Turn Clock T M FEATURES • • XIN/FIN 1 GND 2 CLK0 3 CLK1 4 8 XOUT 7 CLK2,OE,PDB,FSEL 6 NC 5 VDD SOP-8 MSOP-8 CLK1 1 GND 2 XIN/FIN 3 PL611-01 • • • Advanced programmable PLL design Very low Jitter and Phase Noise 30-70ps Pk-Pk typical	Original	PDF	PL611-01 30-70ps 200MHz 10MHz-30MHz 75MHz 200MHz PL611-01 marking code PDB PL611-01-XXXMC PL611-01-XXXSC
Untitled Abstract: No abstract text available Text: Content BOWEI INTEGRATED CIRCUITS CO.,LTD. l LC Filter Outline Drawings -l Miniature LC Bandpass Filter -l Miniature LC Lowpass Filter -l	Original	PDF	MFSS-30-90 DIP24 MFSS-90-200-4 MFSS-200-400 MFSS-225-512-4 MFSS-400-700-4
k117 Abstract: CT5001 T160-C4 VT30-90 Lorch DIODE S3l Equalizer 4000MHz L16 8pin varactor VT400 Text: BOWEI Content BOWEI INTEGRATED CIRCUITS CO.,LTD. LC Filter Outline Drawings- 2 Miniature LC Bandpass Filter- 9 Miniature LC Lowpass Filter - 15	Original	PDF	90MHz) LBM043A 100MHz, 100MHz LBM017A-85 LBM700A-85 Page55) k117 CT5001 T160-C4 VT30-90 Lorch DIODE S3l Equalizer 4000MHz L16 8pin varactor VT400