Untitled
Abstract: No abstract text available
Text: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89871U BUFFER WITH INTERNAL TERMINATION Final FEATURES DESCRIPTION • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by
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SY89871U
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670ps
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Untitled
Abstract: No abstract text available
Text: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge® ̈ Two matched-delay outputs: • Bank A: undivided pass-through QA
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SY89871U
250ps
670ps
10psPP
M9999-082407
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INTEL+2118+DRAM
Abstract: INTEL 2116 DRAM
Text: Intel Xeon® Processor 5500 Series Datasheet, Volume 2 April 2009 Order Number: 321322-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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DDR3-1066
INTEL+2118+DRAM
INTEL 2116 DRAM
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rohde
Abstract: prbs noise generator TLK2521 TLK2521EVM
Text: SLLA149 – JULY 2003 Refclk Jitter Analysis for the TLK2521 The jitter on the reference clock GTXclk can be a very crucial factor when designing applications with the TLK2521. The TLK2521 has an internal PLL with a certain bandwidth depending on the data rate. Jitter on the Refclk with a frequency below the PLL bandwidth gets
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SLLA149
TLK2521
TLK2521.
TLK2521
rohde
prbs noise generator
TLK2521EVM
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SY89871U
Abstract: SY89871UMI SY89871UMITR SY89874U
Text: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL SY89871U Precision Edge™ PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by
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SY89871U
250ps
670ps
10pspp
M9999-062904
SY89871U
SY89871UMI
SY89871UMITR
SY89874U
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SY89871U
Abstract: SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR
Text: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge® Two matched-delay outputs: • Bank A: undivided pass-through QA
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SY89871U
250ps
670ps
10psPP
M9999-082407
SY89871U
SY89871UMG
SY89871UMGTR
SY89871UMI
SY89871UMITR
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LGA1366
Abstract: 2C41h LGA 1366 Intel socket 1366 PIN LAYOUT
Text: Intel Xeon® Processor 3500 Series Datasheet, Volume 2 March 2009 Document Number: 321344-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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medical00
LGA1366
2C41h
LGA 1366
Intel socket 1366 PIN LAYOUT
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VT1315
Abstract: No abstract text available
Text: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by
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SY89871U
250ps
670ps
10psPP
M9999-052307
VT1315
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LVEL91
Abstract: DL140 MC100EL91 MC100LVEL91 SE540 Nippon capacitors
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard
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MC100LVEL/EL91
MC100LVEL91
MC100EL91
MC100LVEL91
MC100EL91
620ps
LVEL91
DL140
SE540
Nippon capacitors
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SY89871U
Abstract: SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR
Text: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by
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SY89871U
250ps
670ps
10psPP
M9999-110705
SY89871U
SY89871UMG
SY89871UMGTR
SY89871UMI
SY89871UMITR
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2c14h
Abstract: No abstract text available
Text: Intel Xeon® Processor 5500 Series Datasheet, Volume 2 April 2009 Order Number: 321322-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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DDR3-1066
2c14h
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Untitled
Abstract: No abstract text available
Text: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89871U FINAL BUFFER WITH INTERNAL TERMINATION FEATURES • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by 2, 4, 8, 16 > (QB0, QB1)
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SY89871U
250ps
670ps
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Untitled
Abstract: No abstract text available
Text: Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series Datasheet, Volume 2 October 2009 Document Number: 320835-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
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i7-900
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Nippon capacitors
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard
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MC100LVEL/EL91
MC100LVEL91
MC100EL91
MC100EL91
620ps
Nippon capacitors
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Untitled
Abstract: No abstract text available
Text: SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input AC or DC-coupled CML, LVPECL, HSTL or
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SY89871U
SY89871U
622MHz
311MHz,
115MHz,
77MHz,
38MHz
the955-1690
M9999-010512-F
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LT1357
Abstract: LT1360 LT1363 LT1395 LT1812 LT1815
Text: DESIGN FEATURES LT1815: 220MHz, 1500V/µs Amplifier Saves Space and Power by Kris Lokere Introduction The LT1815 is a low power, low distortion single op amp with a 220MHz gain bandwidth product and a 1500V/ µs slew rate. The device operates with supplies from ±2V to ±6V and draws
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LT1815:
220MHz,
LT1815
220MHz
500V/
67dBc
LT1815
OT23-5
OT-23-6
LT1357
LT1360
LT1363
LT1395
LT1812
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple PECL to ECL Translator MC100LVEL91 MC100EL91 The MC100LVEL/EL91 is a triple PECL to ECL translator. The MC100LVEL91 receives low voltage PECL signals and translates them to differential ECL output signals. The MC100EL91 receives standard
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MC100LVEL91
MC100EL91
MC100LVEL/EL91
MC100LVEL91
MC100EL91
620ps
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Untitled
Abstract: No abstract text available
Text: CXB1505Q-Y SONY. Triple Fan-Out Buffer with Common Enable and Differential Output_ Description The CXB1505Q-Y is an ultra high speed monolithic ECL IC, which contains three Line Drivers. Each driver has two paires of differential output pins QnA,
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CXB1505Q-Y
CXB1505Q-Y
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