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    71V536

    Abstract: No abstract text available
    Text: PRELIMINARY 32K x 36 CacheRAM 71V536 3.3V SYNCHRONOUS BURST SRAM WITH PIPELINED OUTPUT Integrated Device Technology, Inc. FEATURES: • 32K x 36 memory configuration • Supports high performance system speed - 120 MHz 5.0ns Clock-to-Data Access . • LBO input selects interleaved or linear burst mode


    Original     		PDF IDT71V536 100-pin IDT71V536 648-bit 71V536 PK100-1) 71V536

    71V536

    Abstract: No abstract text available
    Text: PRELIMINARY 32K X 36 CacheRAM 71V536 3.3V SYNCHRONOUS BURST SRAM WITH PIPELINED OUTPUT I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • • • • • • 32K x 36 m em ory configuration Supports high perform ance system speed -1 2 0 MHz


    OCR Scan     		PDF IDT71V536 100-pin 492-M 71V536