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    74LS109A Search Results

    74LS109A Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS109ADR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments
    SN74LS109ANSR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SO 0 to 70 Visit Texas Instruments Buy
    SN74LS109AD Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74LS109ANE4 Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS109AN Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
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    74LS109A Price and Stock

    Texas Instruments SN74LS109ANSR

    IC FF JK TYPE DUAL 1BIT 16SO
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109ANSR Cut Tape 1,880 1
    • 1 $1.5
    • 10 $1.098
    • 100 $0.8849
    • 1000 $0.77312
    • 10000 $0.77312
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    SN74LS109ANSR Digi-Reel 1,880 1
    • 1 $1.5
    • 10 $1.098
    • 100 $0.8849
    • 1000 $0.77312
    • 10000 $0.77312
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    SN74LS109ANSR Reel 2,000
    • 1 -
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    • 100 -
    • 1000 -
    • 10000 $0.71456
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    Mouser Electronics SN74LS109ANSR
    • 1 -
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    • 100 -
    • 1000 -
    • 10000 $0.714
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    Rochester Electronics SN74LS109ANSR 20,000 1
    • 1 $0.7403
    • 10 $0.7403
    • 100 $0.6959
    • 1000 $0.6293
    • 10000 $0.6293
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    Texas Instruments SN74LS109AD

    IC FF JK TYPE DUAL 1BIT 16SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109AD Tube 569 1
    • 1 $1.61
    • 10 $1.177
    • 100 $1.61
    • 1000 $0.85837
    • 10000 $0.85837
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    Rochester Electronics SN74LS109AD 36,742 1
    • 1 $0.7986
    • 10 $0.7986
    • 100 $0.7507
    • 1000 $0.6788
    • 10000 $0.6788
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    Rochester Electronics LLC SN74LS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109AN Tube 375
    • 1 -
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    • 100 -
    • 1000 $0.8
    • 10000 $0.8
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    Rochester Electronics LLC SN74LS109AD

    SN74LS109A DUAL J-K POSITIVE-EDG
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS109AD Bulk 362
    • 1 -
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    • 1000 $0.83
    • 10000 $0.83
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    onsemi DM74LS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey DM74LS109AN Tube 25
    • 1 -
    • 10 -
    • 100 $0.5324
    • 1000 $0.5324
    • 10000 $0.5324
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    Find more 74LS109A price and stock on Findchips.com

    74LS109A Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS109A Signetics Dual J-K Positive Edge-Triggered Flip-Flop Scan PDF
    74LS109A Signetics Flip-Flops Scan PDF

    74LS109A Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    SN54/74LS109A

    Abstract: 751B-03 truth table NOT gate 74 74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A 751B-03 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109 PDF

    74LS109A

    Abstract: SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03 PDF

    JM38510/01405BEA

    Abstract: M38510
    Text: PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/30109B2A ACTIVE LCCC


    Original     		31-May-2014 JM38510/30109B2A JM38510/ 30109B2A JM38510/30109BEA 30109BEA JM38510/01405BEA M38510 PDF

    7054F

    Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
    Text: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver


    Original     		2sc4537 2sc454. 2sc4591 2sc4592 2sc4593 2sc460. 2sc4628 2sc4629 2sc4643 2sc4680 7054F BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557 PDF

    74LS109A

    Abstract: SN54/74LS109A truth table NOT gate 74
    Text: M M O T O R O L A SN54/74LS109A D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 0 9 A c o n s is ts of tw o hig h speed c o m p le te ly in d e p e n d e n t tra n s itio n clo cked J K flip -flo p s . T he clo c k in g o p e ra tio n is in d e p e n d e n t o f rise and fa ll tim e s o f th e c lo c k w a v e fo rm . The


    OCR Scan     		SN54LS/74LS109A SN54/74LS109A Inp125 74LS109A SN54/74LS109A truth table NOT gate 74 PDF

    Untitled

    Abstract: No abstract text available
    Text: M M O TO R O LA SN54/74LS109A D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 10 9 A consists o f tw o high speed com pletely independent tra n sitio n clocked JK flip-flops. The clocking operation is independent of rise and fa ll tim es o f th e d o c k w aveform . The


    OCR Scan     		SN54/74LS109A PDF

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­


    OCR Scan     		GD54/74LS109A PDF

    74ls109

    Abstract: No abstract text available
    Text: MOTOROLA SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP T h e S N 5 4 /7 4 L S 1 0 9 A c o n sists of tw o high sp e e d c o m p le te ly in d e p e n d e n t tra n s itio n clo cke d JK flip -flo p s. T h e c lo c k in g o p e ra tio n is in d e p e n d e n t o f rise


    OCR Scan     		SN54/74LS109A 751B-03 74ls109 PDF

    74LSOO

    Abstract: HD74LS109A
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fr o c k C lock fre q u e n c y C lo c k High P u ls e w idth S r'.v lo w “ H " D a ta S e tu p tim e


    OCR Scan     		HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO HD74LS109A PDF

    RS flip flop IC

    Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
    Text: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The 74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits


    OCR Scan     		M74LS109AP M74LS109AP 16-PIN 20-PIN RS flip flop IC T flip flop pin configuration Toggle flip flop IC JK flip flop IC toggle type flip flop ic PDF

    74LS109AP

    Abstract: M74LS109 flip flop RS M74LS109AP
    Text: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The 74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits


    OCR Scan     		74LS109A M74LS109AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS109AP M74LS109 flip flop RS PDF

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)


    OCR Scan     		74LS109A T-90-10 74LSOO ib203 PDF

    74LSOO

    Abstract: 1S2074 HD74LS109A HD74LS109
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fro c k C lock fre q u e n c y C lo c k High P u ls e w idth Sr.*.v* low “ H " D a ta S e tu p tim e


    OCR Scan     		HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO 1S2074 HD74LS109A HD74LS109 PDF

    pin diagram of 74109

    Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,


    OCR Scan     		LS109A 1N916, 1N3064, 500ns pin diagram of 74109 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54109, SN54LS109A, SN74109, 74LS109A DUAL J-K POSITIVE-EDGE TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR DECEMBER 1983 - REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic


    OCR Scan     		SN54109, SN54LS109A, SN74109, SN74LS109A PDF

    SN74109

    Abstract: LS109A SN54109 SN54LS109A SN74 SN74LS109A rv101
    Text: SN54109, SN54LS109A, SN74109, 74LS109A d u a l j k p o sitiv e e d ge -trigge re d flip -flo p s w ith p re se t and c le a r s d l s 037 DECEMBER 1 9 8 3 - • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic


    OCR Scan     		sn54109, sn54ls109a, sn74109, sn74ls109a sdls037 SN74109 LS109A SN54109 SN54LS109A SN74 SN74LS109A rv101 PDF

    EATON CM20A

    Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
    Text: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main


    OCR Scan     		PDF

    BPW22A

    Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
    Text: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey


    OCR Scan     		BS9000, D3007 HE4000B 80RIBUTION BS9000 BPW22A cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8 PDF

    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


    OCR Scan     		PDF

    TTL 74109

    Abstract: PIN CONFIGURATION 74109 853051 8530510 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, Set and Reset inputs; also com­ plementary Q and 5 outputs.


    OCR Scan     		LS109A 1N916, 1N3064, 500ns 500ns TTL 74109 PIN CONFIGURATION 74109 853051 8530510 74LS109A PDF

    sn 74373

    Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
    Text: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher


    OCR Scan     		PDF

    LG color tv Circuit Diagram schematics

    Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
    Text: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS


    OCR Scan     		MIL-M-38510 38510/MACH 3186J Z501201 Z012510 Z011510 D022110 D022130 D021110 D021130 LG color tv Circuit Diagram schematics texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243 PDF

    54LS109

    Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN J16A M16A
    Text: E M IC D N D U C T O R t General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. T he triggering occurs at a vo lt­


    OCR Scan     		DM74LS109A 16-Lead DM74LS109AN 54LS109FMQB DM54LS109AW 54LS109 54LS109DMQB DM54LS109AJ DM74LS109A J16A M16A PDF

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c PDF