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    74LS112A Search Results

    74LS112A Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS112ANSR Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70 Visit Texas Instruments Buy
    SN74LS112AN Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74LS112ADR Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 Visit Texas Instruments Buy
    SN74LS112AD Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70 Visit Texas Instruments Buy
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    74LS112A Price and Stock

    Texas Instruments SN74LS112ANSR

    Flip Flops Dual Neg-Edge-Trig J-K Flip-Flop
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics SN74LS112ANSR 1,916
    • 1 $0.78
    • 10 $0.5
    • 100 $0.409
    • 1000 $0.377
    • 10000 $0.337
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    Texas Instruments SN74LS112ADR

    Flip Flops Dual Neg-Edge-Trig J-K Flip-Flop
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    Mouser Electronics SN74LS112ADR 689
    • 1 $0.77
    • 10 $0.745
    • 100 $0.745
    • 1000 $0.432
    • 10000 $0.271
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    Texas Instruments SN74LS112AN

    Flip Flops Dual Neg-Edge-Trig J-K Flip-Flop
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    Mouser Electronics SN74LS112AN
    • 1 $0.81
    • 10 $0.518
    • 100 $0.424
    • 1000 $0.39
    • 10000 $0.359
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    Quest Components SN74LS112AN 1,260
    • 1 $0.7
    • 10 $0.7
    • 100 $0.7
    • 1000 $0.28
    • 10000 $0.28
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    SN74LS112AN 36
    • 1 $0.805
    • 10 $0.644
    • 100 $0.4025
    • 1000 $0.4025
    • 10000 $0.4025
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    SN74LS112AN 32
    • 1 $2.4
    • 10 $1.8
    • 100 $1.5
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    SN74LS112AN 8
    • 1 $0.42
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    SN74LS112AN 2
    • 1 $0.805
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    Semiconductors 74LS112A

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com 74LS112A 1,087
    • 1 $2.85
    • 10 $2.85
    • 100 $1.21
    • 1000 $0.443
    • 10000 $0.443
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    Texas Instruments SN74LS112AD

    IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,SOP,16PIN,PLASTIC (Also Known As: 74LS112AD)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components SN74LS112AD 1,600
    • 1 $0.75
    • 10 $0.75
    • 100 $0.75
    • 1000 $0.3
    • 10000 $0.3
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    SN74LS112AD 1,600
    • 1 $0.75
    • 10 $0.75
    • 100 $0.75
    • 1000 $0.3
    • 10000 $0.3
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    SN74LS112AD 124
    • 1 $0.75
    • 10 $0.6
    • 100 $0.45
    • 1000 $0.45
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    SN74LS112AD 24
    • 1 $0.56
    • 10 $0.448
    • 100 $0.448
    • 1000 $0.448
    • 10000 $0.448
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    Find more 74LS112A price and stock on Findchips.com

    74LS112A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS112A

    Abstract: 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16
    Text: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the


    Original     		PDF SN54/74LS112A 74LS112A 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16

    74ls112a

    Abstract: SN54/74LS112A SN54LSXXXJ SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the


    Original     		PDF SN54/74LS112A 74LS112A SN54/74LS112A SN54LSXXXJ SN74LSXXXD SN74LSXXXN

    Untitled

    Abstract: No abstract text available
    Text: PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/07102BEA ACTIVE CDIP


    Original     		PDF 10-Jun-2014 JM38510/07102BEA JM38510/07102B JM38510/07102BFA JM38510/ 07102BFA JM38510/30103B2A 30103B2A JM38510/30103BEA

    Untitled

    Abstract: No abstract text available
    Text: PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) JM38510/07102BEA ACTIVE CDIP


    Original     		PDF 11-Apr-2013 JM38510/07102BEA JM38510/07102B JM38510/07102BFA JM38510/ 07102BFA JM38510/30103B2A 30103B2A JM38510/30103BEA

    Untitled

    Abstract: No abstract text available
    Text: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE


    OCR Scan     		PDF 54LS112A 74LS112A

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M 74LS112AP DUAL J-K N EG A TIVE EDGE-TRIGGERED F L IP FLOPS W IT H SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs


    OCR Scan     		PDF 74LS112AP b2LHfl27 0013Sbl

    74LS112A

    Abstract: No abstract text available
    Text: M MOTOROLA SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the


    OCR Scan     		PDF SN54/74LS112A 54/74LS112A 74LS112A

    M74LS112AP

    Abstract: JK flip flop IC flip flop T Toggle flip flop IC T flip flop IC toggle type flip flop ic M74LS76AP 20-PIN 2V75V
    Text: M IT S U B IS H I LSTTLs M 74LS112AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS W ITH SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs


    OCR Scan     		PDF M74LS112AP M74LS112AP 16-PIN 20-PIN JK flip flop IC flip flop T Toggle flip flop IC T flip flop IC toggle type flip flop ic M74LS76AP 2V75V

    74LS112A

    Abstract: No abstract text available
    Text: M JW 0 T 0 f3 0 1 .X SN54/74LS112A D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 1 1 2 A d u a l J K flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. W h en the c lock goes HIGH, the inputs are enabled and data


    OCR Scan     		PDF SN54/74LS112A 74LS112A

    C350AVB

    Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
    Text: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices


    OCR Scan     		PDF 37MT7bH 74LS175 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A C350AVB full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder

    74LS112AN

    Abstract: 74LS112AM
    Text: I R C H I L D S E M I C O N D U C T O R TM 74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary


    OCR Scan     		PDF DM74LS112A DM74LS112A 74LS112AN 74LS112AM

    EATON CM20A

    Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
    Text: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main


    OCR Scan     		PDF

    54LS112

    Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A
    Text: S E M IC O N D U C T O R tm 74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary


    OCR Scan     		PDF DM74LS112A 54LS112 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A

    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


    OCR Scan     		PDF

    54s112

    Abstract: 74LS112A 74S112
    Text: SN54LS112A, SN54S112, 74LS112A. SN74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A. SN74S112A 54S112, 54s112 74LS112A 74S112

    LS112A

    Abstract: SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A SN74S112A
    Text: SN5 4 L S 112A, SN5 4 S 112, SN7 4 L S 112A, SN7 4 S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET AND CLEAR D 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance S N 5 4 L S 1 1 2 A . S N 5 4 S 1 1 2 . . . J OR W P A C K A G E


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A, SN74S112A LS112A SN54LS112 SN54LS112A SN54S112 SN74 SN74LS112A

    74LS324

    Abstract: 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74C923 equivalent Flip-Flop 7473 74LS324 equivalent 74C08 equivalent
    Text: N T E ELECTRONICS INC 17E H ^3125=1 G0G513S Q B - o S V. ! - TRANSISTOR-TRANSISTOR LOGIC INCLUDES SERIES 74C CMOS NTE TYPE NO. •DESCRIPTION . 7214 7400 74C00 74H00 74LS00 74S00 3-State Sel/Mlpx Quad 2-Input Pos Quad 2-Input Pos Quad 2-Input Pos Quad 2-Input Pos


    OCR Scan     		PDF G0G513S 74C00 74H00 74LS00 74S00 74H01 74LS01 74C02 74LS02 74S02 74LS324 7400 TTL 74LS327 7402, 7404, 7408, 7432, 7400 80C96 74251 multiplexer 74C923 equivalent Flip-Flop 7473 74LS324 equivalent 74C08 equivalent

    SN74LS112

    Abstract: SN54LS112A SN54S112 SN74LS112A SN74S112A SN54L5112A 5S012
    Text: SN54LS112A, SN54S112, SN74 LS112A , SN74 S 112 A D U A L J-K NE GAT IVE EDGE-TRIGGERED FLIP FLO P S WITH PR ESE T AN D CLEA R SDLS011 D 2 6 6 1 , APRIL 1 9 8 2 —REVISED M A R C H 1 9 8 8 • Fully Buffered to Offer Maximum Isolation from External Disturbance


    OCR Scan     		PDF SDLS011 SN54LS112A, SN54S112, SN74LS112A, SN74S112A D2661, 1982-AEVlSED SN74LS112 SN54LS112A SN54S112 SN74LS112A SN54L5112A 5S012

    74LS82

    Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
    Text: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC


    OCR Scan     		PDF

    SN74S112

    Abstract: LS112A S112 SN54LS112A SN54S112 SN74 SN74LS112A CU12B
    Text: TYPES SN54LS112A, SN54S112, 74LS112A, SN74S112 DUAL J -K NEG ATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR ^ _ Fully Buffered to O ffer M a xim u m Isolation from External Disturbance • R E V IS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 1 1 2 A , S N 5 4 S 1 1 2 . . . J OR W P AC KA G E


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A, SN74S112 LS112A S112 SN54LS112A SN54S112 SN74 SN74LS112A CU12B

    74191, 74192, 74193 circuit diagram

    Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
    Text: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and


    OCR Scan     		PDF HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411

    UAA2001

    Abstract: MC8500 micromodule m68mm19 1N9388 74ALS643 2N6058 MC145026 2N5160 MOTOROLA MC3340 equivalent pn3402
    Text: MOTOROLA Semiconductors THE EUROPEAN MASTER SELECTION 1982 The total num ber of standard Sem iconductor products available from M otorola ex­ ceeds 15 0 0 0 device types. To most of our custom ers this total presents an overw helm ing choice. The European Master Selection lists approxim ately 4 0 0 0 preferred devices that re­


    OCR Scan     		PDF 0HF40 0HF60 0HF80 6FP10 6F100 70HF10 UAA2001 MC8500 micromodule m68mm19 1N9388 74ALS643 2N6058 MC145026 2N5160 MOTOROLA MC3340 equivalent pn3402

    74LS382

    Abstract: C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381
    Text: ix u jD U Lu ra n ctiu F U JIT S U _ mmm CWiOS Gate Array GENERAL INFORMATION The Fujitsu CMOS gate array family consists of twentyeight devlcs types which are fabricated with advanced silicon gate CMOS technology. And more than 14devlc«s are coming. Fujitsu CMOS gate array are configured In a


    OCR Scan     		PDF veF178 74LS181 74LS190 F191H 74LS191 74LS192 74LS193 74LS194A 74LS195A 74S260 74LS382 C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381

    74LS167

    Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
    Text: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.


    OCR Scan     		PDF 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74S260 74LS261 74LS167 F199 transistor 74LS382 74LS514 74LS76A transistor b1100 74LS204 74ls171 F199