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Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C4255V Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V Text: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to	Original	CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 8K/16K/32K/64Kx18 CY7C4255/65/75/85V CY7C42X5V CY7C4255V CY7C4265V CY7C4275V CY7C4285V	PDF
CY7C4255 Abstract: CY7C4265 CY7C42X5 Text: CY7C4255 CY7C4265 8K/16K x 18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide	Original	CY7C4255 CY7C4265 8K/16K CY7C42X5 CY7C4255/65 CY7C4255) CY7C4265) 100-MHz 10-ns CY7C4255 CY7C4265	PDF
723653 Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260 Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide	Original	512-bit 16K-bit 64K-bit 128K-bit 256K-bit 512K-bit 100MHz 133MHz 723653 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260	PDF
723653 Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290 Text: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide	Original	512-bit 16K-bit 64K-bit 128K-bit 512K-bit 7236x3/72V36x3 723653 BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290	PDF
Untitled Abstract: No abstract text available Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,	Original	IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125	PDF
add round key for aes algorithm Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152 Text: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
SECDED Abstract: EP3SE50 Text: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),	Original	SIII51004-1 320-bit 144-Kbit M144K SECDED EP3SE50	PDF
CE1X Abstract: 70V7339 A12L IDT70V7339 IDT70V7339S Text: HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7339S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks	Original	IDT70V7339S 166MHz 133MHz) 12Gbps SMEN-01-05 CE1X 70V7339 A12L IDT70V7339 IDT70V7339S	PDF
CY7C4255V Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC Text: CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems ■ High speed, low power, first-in first-out FIFO memories	Original	CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 32K/64Kx18 CY7C4255V) CY7C4265V) CY7C4275V) CY7C4255/65/75/85V CY7C42X5V CY7C4255V CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC	PDF
transistor 5503 dm Abstract: hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822 Text: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.2 March 2011 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original	EP3SL50, EP3SL110, EP3SE80. transistor 5503 dm hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822	PDF
PMD 1000 Abstract: IC ax 2008 USB FM PLAYER ,national semiconductor Linear brief lb-3 EP4SGX230KF40 pin DIAGRAM OF DIP TOP 244 PN bc 1024 cq 724 g diode FM transmiter 10PIN fm recevier project report mbp schematic Text: Stratix IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-2.0 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
Untitled Abstract: No abstract text available Text: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.4 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original		PDF
A1GK Abstract: No abstract text available Text: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SIII5V1-1.0 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	1760-pin 760-Pin A1GK	PDF
CY7C4255V Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC Text: CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to	Original	CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 CY7C4255/65/75/85V CY7C42X5V CY7C4255V CY7C4265V CY7C4275V CY7C4285V CY7C42X5V-ASC	PDF

IDT72T18105 Abstract: IDT72T18115 IDT72T18125 IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895 Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,	Original	IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125 IDT72T18105 IDT72T18115 IDT72T18125 IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895	PDF
CY7C4255 Abstract: CY7C4265 CY7C42X5 only-10 Text: fax id: 5413 1CY 7C42 65 CY7C4255 CY7C4265 PRELIMINARY 8K/16Kx18 Deep Sync FIFOs Features are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can be cascaded to increase FIFO depth. Programmable features	Original	CY7C4255 CY7C4265 8K/16Kx18 CY7C42X5 CY7C4255/65 CY7C4255) CY7C4265) 100-MHz CY7C4255 CY7C4265 only-10	PDF
32kx18 Abstract: No abstract text available Text: 2.5 VOLT HIGH-SPEED TeraSync FIFO PRELIMINARY IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,	Original	IDT72T1845, IDT72T1855 18-BIT/9-BIT IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 IDT72T18125 32kx18	PDF
Untitled Abstract: No abstract text available Text: HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7339S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 8K x 18 banks	Original	IDT70V7339S 166MHz 133MHz) 12Gbps	PDF
LT 543 IC pin diagram Abstract: pin diagram of lt 542 Text: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM \|U \|C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single	OCR Scan	MT56C0818 8Kx18 52-Pin LT 543 IC pin diagram pin diagram of lt 542	PDF
block diagram of 486 Abstract: No abstract text available Text: QS88181 Q High-Speed CMOS 8Kx18 Burst Mode SRAM . « i l a , with Address Counter QS88181 ,I w bdM ,!;Aî TÏ,I OoIN Nf Fo OaR FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondary cache 1 clock initial access + 1 clock/word 40, 33, 25 MHz clock frequency	OCR Scan	QS88181 8Kx18 8Kx18with 52-pin 52pin AO-12 D8-15 block diagram of 486	PDF
Untitled Abstract: No abstract text available Text: M IC R O N * MT56C2818 8 K x 18, DUAL 4 K x 18 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • A u tom atic W RITE cycle com pletion • O p erates a s tw o 4K x 18 SR A M s w ith com m on	OCR Scan	MT56C2818 8Kx18 4KX18SRAM	PDF
Untitled Abstract: No abstract text available Text: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM	OCR Scan	MT56C3818 8Kx18 4KX18SRAM A0-A12) 52-Pin	PDF
block diagram of 486 Abstract: sram with address counter Text: QS88181 Q High-Speed CMOS_ o _ r _ _ _ _ _ _ 8Kx18 Burst Mode SRAM with Address Counter QS88181 « n \/A M rc ADVANCE INFORMATION FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondarycache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency	OCR Scan	QS88181 8Kx18 8Kx18with 52-pin 52pin AO-12 D8-15 block diagram of 486 sram with address counter	PDF
sram with address counter Abstract: RISC and CISC COUNTER LOAD Text: QS88181 Q High-Speed CMOS_ _ w _ r _ 8Kx18 Burst Mode SRAM with Address Counter Q S88181 a ni/ ADVANCE IN FO R M A TIO N F E A T U R E S /B E N E F IT S • • • • 8Kx18with burst mode for secondary cache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency	OCR Scan	QS88181 8Kx18 QS88181 8Kx18with 52-pin AO-12 D8-15 sram with address counter RISC and CISC COUNTER LOAD	PDF

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8KX18 Datasheets Context Search

CY7C4255V

CY7C4255

723653

723653

Untitled

add round key for aes algorithm

SECDED

CE1X

CY7C4255V

transistor 5503 dm

PMD 1000

Untitled

A1GK

CY7C4255V

IDT72T18105

CY7C4255

32kx18

Untitled

LT 543 IC pin diagram

block diagram of 486

Untitled

Untitled

block diagram of 486

sram with address counter