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Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency Configurations Features • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:	Original	PDF	CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit 550-MHz CY7C1163KV18
Untitled Abstract: No abstract text available Text: CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:	Original	PDF	CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit 550-MHz CY7C1163KV18
Untitled Abstract: No abstract text available Text: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C1163KV18/CY7C1165KV18 18-Mbit 550-MHz CY7C1165KV18
3M Touch Systems Abstract: No abstract text available Text: CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C1163KV18, CY7C1165KV18 18-Mbit CY7C1163KV18 550-MHz 3M Touch Systems