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    CY7C1270XV18 Search Results

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    CY7C1270XV18 Price and Stock

    Infineon Technologies AG CY7C1270XV18-633BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1270XV18-633BZXC Tray 680
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    Avnet Americas CY7C1270XV18-633BZXC Tray 11 Weeks 680
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    Rochester Electronics LLC CY7C1270XV18-633BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1270XV18-633BZXC Bulk 3
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    Rochester Electronics LLC CY7C1270XV18-600BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1270XV18-600BZXC Tray 3
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    Infineon Technologies AG CY7C1270XV18-600BZXC

    IC SRAM 36MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1270XV18-600BZXC Tray
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    Cypress Semiconductor CY7C1270XV18-633BZXC

    SRAM Chip Sync Single 1.8V 36M-bit 1M x 36 0.45ns 165-Pin FBGA Tray
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    Verical CY7C1270XV18-633BZXC 130 3
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    Rochester Electronics CY7C1270XV18-633BZXC 130 1
    • 1 $101.81
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    • 100 $95.7
    • 1000 $86.54
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    CY7C1270XV18 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1270XV18-600BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 600MHZ 165FBGA Original PDF
    CY7C1270XV18-633BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 633MHZ 165FBGA Original PDF

    CY7C1270XV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1268XV18/CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original
    PDF CY7C1268XV18/CY7C1270XV18 36-Mbit CY7C1268XV18 CY7C1270XV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)


    Original
    PDF CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original
    PDF CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1268XV18, CY7C1270XV18 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)


    Original
    PDF CY7C1268XV18, CY7C1270XV18 36-Mbit CY7C1268XV18 3M Touch Systems