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    HD74HC27 Search Results

    HD74HC27 Result Highlights (1)

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    HD74HC273RP Renesas Electronics Corporation Octal D-Type Flip-Flops (with Clear), , / Visit Renesas Electronics Corporation
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    HD74HC27 Price and Stock

    Texas Instruments SN74HC273PWR

    Flip Flops Octal w/ Clear
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    Mouser Electronics SN74HC273PWR 13,276
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    Texas Instruments CD74HC27M96

    Logic Gates Hi-Speed CMOS Logic 3 3-Input NOR Gate
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    Mouser Electronics CD74HC27M96 2,783
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    Texas Instruments SN74HC273NSR

    Flip Flops Octal D-Type Flip-Flop w/Clear
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    Mouser Electronics SN74HC273NSR 2,705
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    Texas Instruments SN74HC27NSR

    Logic Gates Triple 3-Input
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    Mouser Electronics SN74HC27NSR 1,417
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    Texas Instruments CD74HC27E

    Logic Gates HS Triple 3-Input
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    Mouser Electronics CD74HC27E 992
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    HD74HC27 Datasheets (30)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HD74HC27 Hitachi Semiconductor Triple 3-Input NOR Gates Original PDF
    HD74HC27 Renesas Technology Triple 3-input NOR Gates Original PDF
    HD74HC273 Hitachi Semiconductor Octal D-type Flip-Flops (with Clear) Original PDF
    HD74HC273 Renesas Technology Original PDF
    HD74HC273FP Renesas Technology Octal D-type Edge-triggered Flip-Flops with Clear Original PDF
    HD74HC273FP Renesas Technology Logic IC; Function: Octal D-type Edge-triggered Flip-Flops with Clear; Package: SOP Original PDF
    HD74HC273P Renesas Technology Octal D-type Edge-triggered Flip-Flops with Clear Original PDF
    HD74HC273P Renesas Technology Logic IC; Function: Octal D-type Edge-triggered Flip-Flops with Clear; Package: DIP Original PDF
    HD74HC273RP Renesas Technology Flip-Flop, Positive-Edge, D Flip-Flop, 8-Element, 1-Input, 20-SOP Original PDF
    HD74HC273RP Renesas Technology Logic IC; Function: Octal D-type Edge-triggered Flip-Flops with Clear; Package: SOP Original PDF
    HD74HC273T Renesas Technology Octal D-type Edge-triggered Flip-Flops with Clear Original PDF
    HD74HC273T Renesas Technology Logic IC; Function: Octal D-type Edge-triggered Flip-Flops with Clear; Package: TSSOP Original PDF
    HD74HC279 Hitachi Semiconductor Quad. S-R Latches Original PDF
    HD74HC279 Renesas Technology Quad. S-R Latches Original PDF
    HD74HC279FP Renesas Technology Latch, SR-Type, Transparent, 4-Channel, 16-SOP Original PDF
    HD74HC279FP Renesas Technology Quad. S-R Latches Original PDF
    HD74HC279P Renesas Technology Latch, SR-Type, Transparent, 4-Channel, 16-DIP Original PDF
    HD74HC279RP Renesas Technology Latch, SR-Type, Transparent, 4-Channel, 16-SOP Original PDF
    HD74HC279RP Renesas Technology Quad. S-R Latches Original PDF
    HD74HC279T Hitachi Semiconductor Latch, SR-Type, Transparent, 4-Channel, 16-TSSOP Original PDF

    HD74HC27 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    HD74HC27

    Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN
    Text: HD74HC27 Triple 3-input NOR Gates ADE-205-415 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max


    Original     		PDF HD74HC27 ADE-205-415 HD74HC27 Hitachi DSA0095 DP-14 FP-14DA FP-14DN

    HD74HC279

    Abstract: HD74HC279FPEL PRSP0016DG-A PRSP0016DH-B
    Text: HD74HC279 Octal D-type Flip-Flops with Clear REJ03D0605–0200 (Previous ADE-205-483) Rev.2.00 Jan 31, 2006 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated


    Original     		PDF HD74HC279 REJ03D0605 ADE-205-483) HD74HC279 HD74HC279FPEL PRSP0016DG-A PRSP0016DH-B

    HD74HC273P

    Abstract: No abstract text available
    Text: HD74HC273 Octal D-type Flip-Flops with Clear REJ03D0604-0200 Rev.2.00 Nov 04, 2008 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear


    Original     		PDF HD74HC273 REJ03D0604-0200 HD74HC273P

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)


    Original     		PDF HD74HC27 Hitachi DSA00279

    HD74HC279

    Abstract: DSA003717 Hitachi DSA003717
    Text: HD74HC279 Quad. S–R Latches Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low,


    Original     		PDF HD74HC279 HD74HC279 DSA003717 Hitachi DSA003717

    HD74HC27

    Abstract: HD74HC27FPEL HD74HC27P PRDP0014AB-B PRSP0014DF-B
    Text: HD74HC27 Triple 3-input NOR Gates REJ03D0543-0200 Previous ADE-205-415 Rev.2.00 Oct 06, 2005 Features • • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V


    Original     		PDF HD74HC27 REJ03D0543-0200 ADE-205-415) PRDP0014AB-B DP-14AV) HD74HC27P DILP-14 HD74HC27FPEL OP-14 HD74HC27RPEL HD74HC27 HD74HC27FPEL HD74HC27P PRDP0014AB-B PRSP0014DF-B

    HD74HC273

    Abstract: Hitachi DSA00389
    Text: HD74HC273 Octal D-type Flip-Flops with Clear Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition


    Original     		PDF HD74HC273 HD74HC273 Hitachi DSA00389

    Untitled

    Abstract: No abstract text available
    Text: HD74HC279 Octal D-type Flip-Flops with Clear REJ03D0605–0200 (Previous ADE-205-483) Rev.2.00 Jan 31, 2006 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated


    Original     		PDF HD74HC279 REJ03D0605â ADE-205-483)

    DP-14

    Abstract: FP-14DA FP-14DN HD74HC27 Hitachi DSA00386
    Text: HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)


    Original     		PDF HD74HC27 DP-14 FP-14DA FP-14DN HD74HC27 Hitachi DSA00386

    HD74HC273P

    Abstract: HD74HC273RPEL HD74HC273 HD74HC273TELL HD74HC273FPEL PRDP0020AC-B PRSP0020DD-B TSSOP-20
    Text: HD74HC273 Octal D-type Flip-Flops with Clear REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear


    Original     		PDF HD74HC273 REJ03D0604-0300 HD74HC273P HD74HC273RPEL HD74HC273 HD74HC273TELL HD74HC273FPEL PRDP0020AC-B PRSP0020DD-B TSSOP-20

    HD74HC273

    Abstract: Hitachi DSA00222
    Text: HD74HC273 Octal D-type Flip-Flops with Clear ADE-205-482 (Z) 1st. Edition Sep. 2000 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition


    Original     		PDF HD74HC273 ADE-205-482 HD74HC273 Hitachi DSA00222

    HD74HC279

    Abstract: Hitachi DSA00222
    Text: HD74HC279 Quad. S–R Latches ADE-205-483 Z 1st. Edition Sep. 2000 Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is


    Original     		PDF HD74HC279 ADE-205-483 HD74HC279 Hitachi DSA00222

    Untitled

    Abstract: No abstract text available
    Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid


    Original     		PDF

    HD74HC273P

    Abstract: HD74HC273 HD74HC273FPEL HD74HC273RPEL HD74HC273TELL PRDP0020AC-B PRSP0020DD-B TSSOP-20
    Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74HC27 # Triple 3-input NOR Gates • FEATURES I • High Speed O peration: tp rf“ 10n» ty p . Q _” 50pF • High O u tp u t C urrent: Fanout o f 10 L S T T L Load« • Wide O perating Voltage: Vcc” 2 ~ 6V • Low In p u t C urrent: 1>iA max. • L o w Q uietcent Supply C urrent: icc (static) ■■1mA max. (T « « 2 5 “ C)


    OCR Scan     		PDF HD74HC27 --20/uA --20/1A -50pF, o--25

    Untitled

    Abstract: No abstract text available
    Text: HD74HC27 • Triple 3-input NOR Gates • FEATURES I PIN ARR ANG E M E NT • High Speed Operation: tpc/= 10ns ty p . C/_ = 50 p F Vcc • High O u tp u t Current: Fanout of 10 L S T T L Loads 1C • Wide Operating Voltage: l/'cc = 2 ~ 6 V • Low In put C urrent: 1/iA max.


    OCR Scan     		PDF HD74HC27

    74hc273

    Abstract: No abstract text available
    Text: HD74HC273 # Octal D-type Flip-Flops with Clear This device contains 8 master-slave flip-flops with a common | PIN ARRANGEMENT clock and common clear. Data on the D input having the “W specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear


    OCR Scan     		PDF HD74HC273 7o--40~ 74hc273

    Untitled

    Abstract: No abstract text available
    Text: HD74HC279 # Quad. S —R Latches PIN ARRANGEMENT The latch is ideally suited for use as tem porary stage for binary information processing and input/output units.W hen either S or R is low , output is dependent on R input. W hen both inputs are high, O utput is stored before the indicated steadystate input conditions were established. A nd w hen both


    OCR Scan     		PDF HD74HC279

    Untitled

    Abstract: No abstract text available
    Text: HD74HC27 % Triple 3-input NOR Gates • FEATURES • • • • • I PIN ARRANGEMENT High Speed Operation: tp^=10ns typ. Cf»50pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: Vcc~2 ~ 6 V Low Input Current: 1*tA max. Low Quiescent Supply Current: Icc (static) ■ 1mA max. (ra«2 6 °C )


    OCR Scan     		PDF HD74HC27 max13 -50pF,

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT


    OCR Scan     		PDF HD74HC273 44Tb2Q3 0D1D315 T-90-20

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/ARRAYS/MEM T5 0G1G334 92D HD74HC27 # 10334 d fl J ~ T '^ 3 " 2 -/ Triple 3-input NOR Gates • FEATURES • High Speed Operation: 10ns typ. Ci.«50pF • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: l/c c * 2 ~ 6 V


    OCR Scan     		PDF 0G1G334 HD74HC27 44IitiED3 0D1D315 T-90-20

    Untitled

    Abstract: No abstract text available
    Text: HD74HC279 Quad. S —R Latches The Latch is ideally suited for use as temporary stage for binary Information processing and input/output units.W hen either S or R is low , output is dependent on R input. W hen both inputs are high. Output is stored before the indicated steadystate input conditions were established. And when both


    OCR Scan     		PDF HD74HC279 20//A --20nA

    Untitled

    Abstract: No abstract text available
    Text: HD74HC279 # Quad. S - R Latches PIN ARRANGEMENT The latch is ideally suited for use as temporary stage for binary information processing and input/output units.When either S or R is low, output is dependent on R input. When both inputs are high. Output is stored before the indicated steadystate input conditions were established. And when both


    OCR Scan     		PDF HD74HC279 20//A Ta--25

    HD74HC273

    Abstract: No abstract text available
    Text: HD74HC273 Octal D-type Flip-Flops with Clear This device contains 8 matter-slave flip-flops »with a common dock and common clear. Oats on the D input having the | PIN ARRANGEMENT specified setup and hold times is transferred to the Q output on the low to high transition of the d ock input. The clear


    OCR Scan     		PDF HD74HC273 HD74HC273