Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    LF3312 Search Results

    LF3312 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    LF3312 Logic Devices 12-Mbit Frame Buffer / FIFO Original PDF
    LF3312 Logic Devices 12 M-bit Frame Buffer/FIFO Original PDF
    LF3312BGC Logic Devices 12-Mbit Frame Buffer / FIFO Original PDF
    LF3312BGC Logic Devices 12-Mbit Frame Buffer / FIFO Original PDF

    LF3312 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 25MHz 10-bit 12-bit 16-bit 20-bit 24-bit

    LF3312

    Abstract: LF3312BGC position sensitive diode circuit
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 25MHz 10-bit 12-bit 16-bit 20-bit 24-bit LF3312 LF3312BGC position sensitive diode circuit

    LF3312

    Abstract: No abstract text available
    Text: Image Manipulation – Vertical Flip LF3312 - Application Note OVERVIEW With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the


    Original     		PDF LF3312 12bit

    LF3312

    Abstract: No abstract text available
    Text: LF3312 Product Brief DEVICES INCORPORATED 12Mbit Frame Buffer / FIFO Providing designers with a single-chip approach to Sequential and Random Data Access FEATURES: Configurable 12,441,600-bit Memory - Allocate as Single/Dual Channels - Selectable Input/Output Word Widths


    Original     		PDF LF3312 12Mbit 600-bit 83Mhz 12Mbit 6/04/2004-LPB 312-A LF3312

    LF3312

    Abstract: DSA00113352
    Text: Image Manipulation - Reflect Image on Vertical Axis DEVICES INCORPORATED Video Memory Application Note FRAME MEMORY Overview With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘mirror image’ of a frame of


    Original     		PDF LF3312 BIN11 BOUT11 DSA00113352

    LF3312

    Abstract: LF3312s LF33 12FC00
    Text: Depth Expansion through Cascading LF3312 - Application Note OVERVIEW Cascading multiple LF3312s for depth expansion is easy. The usable 24bit address space is simply extended for every additional device that is cascaded. The LF3312 is cascaded in parallel, where the input of each device is tied together. The input data


    Original     		PDF LF3312 LF3312s 24bit LF33 12FC00

    LF3312 m

    Abstract: LF3312 LF3312BGC
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 25MHz 10-bit 12-bit 16-bit 20-bit 24-bit LF3312 m LF3312 LF3312BGC

    LF3312

    Abstract: reset
    Text: Hard and Soft Resets - Using RESET Pin LF3312 - Application Note OVERVIEW The RESET pin can both reset the contents of the Configuration Registers back to their default states see datasheet and act as a ‘global W/R pointer reset’. There are two types of resets that can be accomplished using the RESET pin: Hard and Soft resets.


    Original     		PDF LF3312 reset

    LF3312

    Abstract: No abstract text available
    Text: Picture-in-Picture or Multi-source Buffering LF3312 - Application Note OVERVIEW Multiple independent data/video streams can be written into a shared linear address space using multiple LF3312s. Picture in Picture applications can be implemented where multiple video feeds are


    Original     		PDF LF3312 LF3312s. LF3312s 12bit

    LF3312

    Abstract: No abstract text available
    Text: Image Manipulation – Mirror Image LF3312 - Application Note OVERVIEW With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘mirror


    Original     		PDF LF3312 12bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 25MHz 10-bit 12-bit 16-bit 20-bit 24-bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 25MHz 10-bit 12-bit 16-bit 20-bit 24-bit

    Untitled

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information FEATURES 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit

    LF3312

    Abstract: 19 214
    Text: This application brief describes the LF3312’s programmable flag behaviour. The first section describes the Empty/Full threshold settings. The second section provides a simple example of how the flags react to enabled writes and reads to/from the memory.


    Original     		PDF LF3312 731st 439th 440th 19 214

    LF3312

    Abstract: No abstract text available
    Text: Image Manipulation - Reflect Image on Horizontal Axis DEVICES INCORPORATED Video Memory Application Note FRAME MEMORY Overview With the LF3312’s flexible memory address architecture, data can be sequentially stored in memory and then accessed using a completely reordered address. An application such as creating the ‘vertical flip’, or upside-down


    Original     		PDF LF3312 BOUT11 BIN11 AOUT11 24bit

    LF3312

    Abstract: 27MHZ
    Text: Frame Delay of Digital Component Video LF3312 - Application Note OVERVIEW It is sometimes necessary to buffer fields or frames in a completely synchronous, delay-line fashion. This is often the case when comparing the current frame f with previous frames (f-1), (f-2), and so


    Original     		PDF LF3312 10bit 27MHZ

    marking apf

    Abstract: LF3312 LF3312BGC
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit marking apf LF3312 LF3312BGC

    LF3312

    Abstract: No abstract text available
    Text: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Advance Information Features 12,441,600-bit Frame Memory May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel) • 1,036,800 x 12-bit (single channel)


    Original     		PDF LF3312 12-Mbit 600-bit 10-bit 12-bit 16-bit 20-bit 24-bit LF3312

    LF3312

    Abstract: BUFFER FIFO
    Text: OVERVIEW The basis for a frame synch system is managing the distance between Write and Read pointers of a Frame Buffer FIFO such as the LF3312. Frame tearing can easily occur in un-managed frame synchronization systems. Frame tearing occurs as the pointers sweep across each other, sometimes


    Original     		PDF LF3312. LF3312 BUFFER FIFO

    LF3312

    Abstract: VIDEO FRAME LINE BUFFER block DIAGRAM OF random access memory sequential MEMORY line
    Text: De-interlacing – Video Storage LF3312 - Application Note Let the LF3312 Frame Buffer be the storage workhorse for your de-interlacing application. There is an increasing need for high performance de-interlacing systems as we convert more and more media into progressive scan format for consumption. The LF3312 is well


    Original     		PDF LF3312 VIDEO FRAME LINE BUFFER block DIAGRAM OF random access memory sequential MEMORY line

    LF3312

    Abstract: video stream
    Text: Video Synchronization LF3312 - Application Note OVERVIEW The LF3312 is good tool for synchronizing video or data streams with arbitrary timing to a set system or ‘master’ timing source. The timing sources are typically in the form of a Clock and a field/frame


    Original     		PDF LF3312 LF3312s 10bit video stream