74LVQ00
Abstract: 74LVQ00SC 74LVQ00SJ M14A M14D
Text: General Description Features The LVQ00 contains four 2-input NAND gates. n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω
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LVQ00
74LVQ00SC
14-Lead
74LVQ00SJ
14-Lead
E80-530
ds011341
74LVQ00
74LVQ00SC
74LVQ00SJ
M14A
M14D
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74LVQ00
Abstract: 74LVQ00MTR 74LVQ00TTR TSSOP14
Text: lvq00.fm Page 1 Thursday, July 29, 2004 2:28 PM LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C
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lvq00
74LVQ00
74LVQ00
74LVQ00MTR
74LVQ00TTR
TSSOP14
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74LVQ00
Abstract: 74LVQ00SC 74LVQ00SCX 74LVQ00SJ 74LVQ00SJX M14A M14D
Text: LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQ00 contains four 2-input NAND gates Y Y Y Y Y Ideal for low power low noise 3 3V applications Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed pin-to-pin skew AC performance
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74LVQ00
LVQ00
MIL-STD-883
C1996
74LVQ00
74LVQ00SC
74LVQ00SCX
74LVQ00SJ
74LVQ00SJX
M14A
M14D
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74LVQ00
Abstract: 74LVQ00MTR 74LVQ00TTR TSSOP14
Text: lvq00.fm Page 1 Thursday, July 29, 2004 2:28 PM LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C
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lvq00
74LVQ00
74LVQ00
74LVQ00MTR
74LVQ00TTR
TSSOP14
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74LVQ00
Abstract: 74LVQ00SC 74LVQ00SJ M14A M14D
Text: Revised April 2001 LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQ00 contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance
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74LVQ00
LVQ00
74LVQ00SC
14-Lead
MS-012,
74LVQ00SJ
74LVQ00
74LVQ00SC
74LVQ00SJ
M14A
M14D
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74LVQ00
Abstract: 74LVQ00M 74LVQ00T TSSOP14
Text: LVQ00 QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
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74LVQ00
LVQ00
74LVQ00
74LVQ00M
74LVQ00T
TSSOP14
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PDF
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74LVQ00
Abstract: 74LVQ00M 74LVQ00T TSSOP14
Text: LVQ00 QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
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74LVQ00
LVQ00
74LVQ00
74LVQ00M
74LVQ00T
TSSOP14
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PDF
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74LVQ00
Abstract: No abstract text available
Text: LVQ00 QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING
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74LVQ00
74LVQ00M
74LVQ00T
74LVQ00
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Untitled
Abstract: No abstract text available
Text: Æ T S G S -T H O M S O N D lsi S IILICTIs! iD©S LVQ00 QUAD 2-INPUT NAND GATE . HIGH SPEED: tPD = 5.5 ns (TYP.) at V c c = 3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Ice = 2 |xA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at V c c = 3.3V
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OCR Scan
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74LVQ00
LVQ00
P013G
TSS0P14
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LH 036
Abstract: 74LVQ00
Text: S G S -TH O M S O N G l LVQ00 IU QUAD 2-INPUT NAND GATE . HIGH SPEED: tpD = 5.5 ns TYP. at Vcc = 3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Icc = 2 nA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at Vcc = 3.3V . 75i2 TRANSMISSION LINE DRIVING
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OCR Scan
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74LVQ00
74LVQ00M
74LVQ00T
S63-THOmOH
LH 036
74LVQ00
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KHN 10
Abstract: 74LVQ00 74LVQ00M 74LVQ00T TSSOP14 truth table NAND gate 74
Text: SGS-THOMSON LVQ00 M IM i[Li gïïlHΩiD(3S Q UAD 2-IN PUT NAND GATE . HIGH SPEED: tPD = 5.5 ns (TYP.) at V Cc =3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Icc = 2 |xA (MAX.) at T a = 25 °C . LOW NOISE: V o lp = 0.3 V (TYP.) at V Cc = 3.3V
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OCR Scan
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74LVQ00
LVQ00
P013G
TSSOP14
KHN 10
74LVQ00
74LVQ00M
74LVQ00T
truth table NAND gate 74
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74LVQ00
Abstract: No abstract text available
Text: r z 7 Ä T # S G S -T H O M S O N R L E M « ! 74LVQ 00 QUAD 2-INPUT NAND GATE . HIGH SPEED: tPD = 5.5 ns TYP. at Vcc = 3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Icc = 2 jjA (MAX.) at Ta = 25 °C . LOW NOISE: V olp = 0 .3 V (TYP.) at VCc =3.3V
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OCR Scan
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74LVQ
74LVQ00M
74LVQ00T
74LVQ00
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PDF
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74LVQ00
Abstract: No abstract text available
Text: LVQ00 QUAD 2-INPUT NAND GATE . HIGH SPEED: tPD = 5.5 ns TYP. at Vcc = 3.3V • COMPATIBLE WITH TTL OUTPUTS . LOW POWER DISSIPATION: Ice = 2 nA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0 .3 V (TYP.) at V c c = 3 .3 V ■ 75Q TRANSMISSION LINE DRIVING
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OCR Scan
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74LVQ00
74LVQ00M
74LVQ00T
LVQ00
74LVQ00
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Untitled
Abstract: No abstract text available
Text: LVQOO £3 National mm Semiconductor 54LVQ/LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The ’LVQOO contains four 2-inpul NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and
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OCR Scan
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54LVQ/74LVQ00
TL/F/11341-1
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