MBL8392A
Abstract: TRANSFORMER 9V 500 ma MBL8392 10BASE2 10BASE5 MBL8393APD-G MBL8393AP-G
Text: MBL8392A COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATA SHEET FEATURES • Compatible with Ethernet II, IEEE 802.3 10BASE5 and 10BASE2, and ISO 8802/-3 interface specifications • Integrates all active transceiver electronics • Only one external resistor required for setting coaxial
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MBL8392A
10BASE5
10BASE2,
16-pin
28-pin
MBL8392A
TRANSFORMER 9V 500 ma
MBL8392
10BASE2
10BASE5
MBL8393APD-G
MBL8393AP-G
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MB86950 Etherstar Ethernet Controller
Abstract: MB86950 etherstar MB86962 MB86951 CODER MANCHESTER DIFFERENTIAL aui isolation transformer differential manchester encoder manchester encoder 10BASE2
Text: MB86951 CMOS ETHERNET ENCODER/DECODER DATA SHEET FEATURES • 10 Mbit/sec Manchester encoder/decoder • Compatible with IEEE 802.3 10BASE2, 10BASE5 and 10BASE-T specifications • Receiver clock recovery with dual phase locked loop for high stability • Decodes Manchester data with up to ±20 ns of jitter.
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MB86951
10BASE2,
10BASE5
10BASE-T
24-pin
MB86951
MB86950 Etherstar Ethernet Controller
MB86950
etherstar
MB86962
CODER MANCHESTER DIFFERENTIAL
aui isolation transformer
differential manchester encoder
manchester encoder
10BASE2
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PM6501
Abstract: BMPR10 VALOR PM6501 10BASE2 10BASE5 MB86960 MB86961 MB86965 MB84256 150145
Text: MB86965 ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses • Interface to serial EEPROM for Node ID and configuration option storage allows construction of jumperless, electronically configurable adapter cards
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MB86965
10BASE-T
50-mil
MB86965
PM6501
BMPR10
VALOR PM6501
10BASE2
10BASE5
MB86960
MB86961
MB84256
150145
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PM6501
Abstract: PM6501 dc to dc VALOR PM6501 10BASE2 10BASE5 MB86960 MB86961 MB86965 MBL8392A BMPR10
Text: MB86965 ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses • Interface to serial EEPROM for Node ID and configuration option storage allows construction of jumperless, electronically configurable adapter cards
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MB86965
10BASE-T
50-mil
MB86965
PM6501
PM6501 dc to dc
VALOR PM6501
10BASE2
10BASE5
MB86960
MB86961
MBL8392A
BMPR10
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MB86953
Abstract: fault codes for RBS BD10 BD12 MB86960 BUT16
Text: MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET FEATURES • High-performance packet buffer architecture pipelines data for highest throughput • 20 Mbyte/second data transfer rate to/from the system bus • on-chip buffer controller manages pointers, reduces
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MB86960
64-element
100-Pin
MB86960APF-G
MB86953
fault codes for RBS
BD10
BD12
MB86960
BUT16
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xmtd
Abstract: MB86965A 10BASE 10BASE2 10BASE5 MB86965 MB86965B LSA0 memory BMPR18
Text: MB86965A/MB86965B ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET Note: All descriptions apply to both the MB86965A and MB86965B FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses
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MB86965A/MB86965B
MB86965A
MB86965B
10BASE-T
xmtd
10BASE
10BASE2
10BASE5
MB86965
MB86965B
LSA0 memory
BMPR18
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MB502A
Abstract: datasheet HT12 D ht12 decoder MB86960APF-G mb86953 BD10 BD12 MB86960 BUT16
Text: MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET FEATURES • High-performance packet buffer architecture pipelines data for highest throughput • 20 Mbyte/second data transfer rate to/from the system bus • on-chip buffer controller manages pointers, reduces
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MB86960
64-element
100-Pin
MB86960APF-G
100-Lead
FPT-100P-M06)
MB502A
datasheet HT12 D
ht12 decoder
MB86960APF-G
mb86953
BD10
BD12
MB86960
BUT16
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k3525
Abstract: MBL8392A
Text: MBL8392A FUJITSU COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATA SH EET APRIL1993 FEATURES During transmission the jabber timer is initiated to dis able the CTI transmitter in the event of a longer than legal length data packet. Collision detection circuitry
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MBL8392A
APRIL1993
5M-1982.
k3525
MBL8392A
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jrm a40
Abstract: U/25/20/TN26/15/850/tl-130 transformer
Text: MBL8392A FUJITSU COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATASHEET APRILI 993 FEATURES Compatible with Ethernet n , IEEE 802.3 10BASE5 and 10BASE2, and ISO 8802/-3 interface specifica tions Integrates all active transceiver electronics Only one external resistor required for setting coaxial
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MBL8392A
10BASE5
10BASE2,
374T75L.
jrm a40
U/25/20/TN26/15/850/tl-130 transformer
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fujitsu ten connector
Abstract: fujitsu ten lc ns73M SKS 25F CTS100 ht12 decoder
Text: M B 86965 FUJITSU ET H E R C O U P L E R SINGLE-CHIP E T H E R N E T CO N T R O L L E R APRIL1993 DATASHEET F E AT URE S • Provides interface to the I/O bus of PC/XT /AT or compatible computers • Optional, generic hostinterfaceto connect to industrystandard microprocessor buses
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APRIL1993
10BASE-T
FPT-160P-M03)
04S-3C-2
fujitsu ten connector
fujitsu ten lc
ns73M
SKS 25F
CTS100
ht12 decoder
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Untitled
Abstract: No abstract text available
Text: M B86960 F ilim i! NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATASHEET A P R IL I 9 9 3 FEA TU R ES • High-performance packet buffer architecture pipe lines data for highest throughput • 20 Mbyte/second datatransferrate to/from thesystem
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B86960
64-element
MB86960
MB86960APF-G
100-Lead
FPT-100P-M06)
aiL00
374175t.
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Untitled
Abstract: No abstract text available
Text: M B 8 6 9 6 5 A/M B 8 6 9 6 5 B FUJITSU ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATASHEET Note: All descriptions apply to both the M B86965A and MB86965B FEATURES • Provides interface to the I/O bus of PC/XT /AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses
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B86965A
MB86965B
10BASE-T
MB86965_
ootft40i
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Untitled
Abstract: No abstract text available
Text: MB86965 FUJITSU ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATASHEET APRILI 993 FEATURES Provides interface to the I/O bus of PC/XT /AT or compatible computers Optional, generic host interface to connect to industrystandard microprocessor buses Interface to serial EEPROM for Node ID and configu
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MB86965
10BASE-T
37MT75b
MB86965_
001IMD1
374T75L
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fujtsu
Abstract: RBS02 BUT16
Text: MB86960 FUJITSU NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET A P R ILI 993 superior benchmark speed and application performance. The NICE device has a partitionable 2, 4, 8, or 16 kilobyte, two-bank, transmit buffer which allows multiple data packets to be “chained” together and trans
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MB86960
64-element
100-Lead
fujtsu
RBS02
BUT16
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C2650N
Abstract: MB86950 L8392A
Text: MB86951 FUJITSU CMOS ETHERNET ENCODER/DECODER APRILI 993 DATA SHEET balanced differential pair to the transceiver. During receive operation it converts M anchester encoded data on a balanced differential pair from the transceiv er into N R Z data and forw ards it to the controller,
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MB86951
10BASE2,
10BASE5
10BASE-T
24-pin
MB86951PF-G
C2650N
MB86950
L8392A
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pinouts aui db15
Abstract: PM6501 fujitsu ten ECU IC 74ALS245 application 161 0M
Text: M B86965 _ FUJITSU ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA S H E E T A P R IL 1 9 9 3 FEATURES daughter and m otherboards, as w ell as expansion-bus adapter boards. An E E P R O M can be interfaced to the chip for storage o f E thernet ID and configuration set
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B86965
MB86965_
10BASE2
160-LEAD
FPT-160P-MQ3)
pinouts aui db15
PM6501
fujitsu ten ECU
IC 74ALS245 application
161 0M
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Untitled
Abstract: No abstract text available
Text: MB86951_ FUJITSU CMOS ETHERNET ENCODER/DECODER DATASHEET FEATURES • 10 Mbit/sec Manchester encoder/decoder • Compatible with IEEE 802.3 10BASE2,10BASE5 and 10BASE-T specifications • Receiver clock recovery with dual phase locked loop
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MB86951_
10BASE2
10BASE5
10BASE-T
APRIL1993
MB86951
MB86951P-
MB86951
MB86951PF-G
24-LEACi
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Untitled
Abstract: No abstract text available
Text: FUJITSU MB86960 NICE Ethernet Controller FACT SHEET JUNE 1990 DESCRIPTION FEATURES 20 Mbytes/second data transfer rate to the system bus On-chip Buffer Management Unit reduces software overhead High-speed burst and single transfer DMA Bus compatibility for all standard microprocessors
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MB86960
100-pin
MB86960
1690WCGX
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RPY 86
Abstract: BUT16
Text: M B 86960 FUJITSU N E T W O R K INTERFACE CO N T R O L L E R with E N C O D E R / D E C O D E R NICE DATASHEET FEATURES High-performance packet buffer architecture pipe lines data for highest throughput 20 Mbyte/second data transferrate to/from the system
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APRIL1993
64-element
MB86960
100-pin
FPT-100P-M06)
0008-3C-2
RPY 86
BUT16
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Untitled
Abstract: No abstract text available
Text: FUJITSU MB86951 CMOS Ethernet Encoder/Decoder FACT SHEET JUNE 1990 FEATURES DESCRIPTION • The CMOS M B86951 is a functionally complete Serial Network Interface SNI that provides the Manchester data encoding and decoding functions for Ethernet (10BASE5) and Thin Ethernet
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MB86951
B86951
10BASE5)
B86950
MBL8392A
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