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    SN74LV00APWR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LV00ARGYR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-VQFN -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADGVR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-TVSOP -40 to 125 Visit Texas Instruments Buy
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 125 Visit Texas Instruments Buy
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    Texas Instruments SN74LV00APWR

    IC GATE NAND 4CH 2-INP 14TSSOP
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    Texas Instruments SN74LV00AD

    IC GATE NAND 4CH 2-INP 14SOIC
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    DigiKey SN74LV00AD Tube 4,225 1
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    Texas Instruments SN74LV00ANSR

    IC GATE NAND 4CH 2-INP 14SO
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    DigiKey SN74LV00ANSR Digi-Reel 3,990 1
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    Texas Instruments SN74LV00ARGYR

    IC GATE NAND 4CH 2-INP 14VQFN
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    DigiKey SN74LV00ARGYR Digi-Reel 2,880 1
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    Texas Instruments SN74LV00ADR

    IC GATE NAND 4CH 2-INP 14SOIC
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    SN74LV00ADR 3,288
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    SN74LV00 Datasheets (115)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LV00 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00A Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    SN74LV00AD Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SOIC Original PDF
    SN74LV00AD Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00AD Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV00AD Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SOIC -40 to 85 Original PDF
    SN74LV00ADB Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBLE Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBLE Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBLE Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBR Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SSOP Original PDF
    SN74LV00ADBR Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Original PDF
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    SN74LV00ADBR Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBR Texas Instruments SN74LV00 - Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF
    SN74LV00ADBRG4 Texas Instruments Logic - Gates and Inverters, Integrated Circuits (ICs), IC GATE NAND 4CH 2-INP 14-SSOP Original PDF
    SN74LV00ADBRG4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 Original PDF

    SN74LV00 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B


    Original     		SN54LV00A, SN74LV00A SCLS389G SN54LV00A A115-A C101 SN54LV00A SN74LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B


    Original     		SN54LV00A, SN74LV00A SCLS389G SN54LV00A SN74LV00A 000-V A114-A) A115-A) PDF

    SN54LV00A

    Abstract: SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389C – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389C MIL-STD-883, SN54LV00A SN74LV00A PDF

    LV00A

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y


    Original     		SN54LV00A, SN74LV00A SCLS389E SN54LV00A SN74LV00A 000-V A114-A) A115-A) LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A SN74LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    SN54LV00

    Abstract: SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE
    Text: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00, SN74LV00 SCLS182C MIL-STD-883C, JESD-17 300-mil SN54LV00 SN54LV00 SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV00A . . . J OR W PACKAGE


    Original     		SN54LV00A, SN74LV00A SCLS389J SN54LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    SN74LV00

    Abstract: SN54LV00
    Text: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00, SN74LV00 SCLS182C MIL-STD-883C, JESD-17 300-mil SN54LV00 SN74LV00 SN54LV00 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J PDF

    lv00a

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A lv00a PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J 000-V A114-A) A115-A) SN54LV00A PDF

    SN54LV00

    Abstract: SN74LV00
    Text: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00, SN74LV00 SCLS182C MIL-STD-883C, JESD-17 300-mil SN54LV00 SN54LV00 SN74LV00 PDF

    SN54LV00

    Abstract: SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE
    Text: SN54LV00, SN74LV00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS182C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y SN54LV00 . . . FK PACKAGE


    Original     		SN54LV00, SN74LV00 SCLS182C SN54LV00 MIL-STD-883C, 250trollers SN54LV00 SN74LV00 SN74LV00D SN74LV00DBLE SN74LV00DR SN74LV00PWLE PDF

    A115-A

    Abstract: C101 SN54LV00A SN74LV00A
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCLS389J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		SN54LV00A, SN74LV00A SCLS389J A115-A C101 SN54LV00A SN74LV00A PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00A, SN74LV00A QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS389B - SEPTEMBER 1997 - REVISED APRIL 1998 EPIC Enhanced-Performance implanted CMOS Process SN54LVOOA . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		SN54LV00A, SN74LV00A SCLS389B JESD17 MIL-STD-883, 300-mil SN54LVOOA SN74LV00A PDF

    SN74LV00

    Abstract: 122A-4
    Text: SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS1S2A- FEBRUARY 1993-REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-n Process • Typical Volp (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vohv (Output V q h Undershoot)


    OCR Scan     		SN74LV00 SCLS182A-FEBRUARY 1993-REVISED MIL-STD-883C, JESD-17 SN74LV00 122A-4 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LV00, SN74LV00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES _ S C L S 1B 2C -F E B R U A R Y 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process Typical V(j|_p (Output Ground Bounce)« 0.8 V at Vcc> TA = 25°C


    OCR Scan     		SN54LV00, SN74LV00 MIL-STD-883C, JESD-17 300-mil PDF