723674
Abstract: IDT723654 IDT723664 IDT723674
Text: CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2 FEATURES: PRELIMINARY IDT723654 IDT723664 IDT723674 ♦ Port B bus sizing of 36 bits long word , 18 bits (word) and 9 bits (byte) ♦ Big- or Little-Endian format for word and byte bus sizes
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IDT723654
IDT723664
IDT723674
128-pin
PK128-1)
com/docs/PSC4045
723674
IDT723654
IDT723664
IDT723674
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IDT72V3626
Abstract: IDT72V3636 IDT72V3646
Text: 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: PRELIMINARY IDT72V3626 IDT72V3636 IDT72V3646 • Serial or parallel programming of partial flags • Big- or Little-Endian format for word and byte bus sizes
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IDT72V3626
IDT72V3636
IDT72V3646
128-pin
72V3626
72V3636
72V3646
com/docs/PSC4045
IDT72V3626
IDT72V3636
IDT72V3646
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R3000
Abstract: RC3041 RC4640 RC4650 RC5000 CX171 cx55 27C08 CX52 2cy30
Text: Version 1.1 October 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1999 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in
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OSC10Mhz
R3000
RC3041
RC4640
RC4650
RC5000
CX171
cx55
27C08
CX52
2cy30
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IDT723623
Abstract: IDT723633 IDT723643 B35b
Text: CMOS Bus-Matching SyncFIFO 256 x 36, 512 x 36, 1,024 x 36 PRELIMINARY IDT723623 IDT723633 IDT723643 Integrated Device Technology, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:
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IDT723623
IDT723633
IDT723643
IDT723623
IDT723633
IDT723643
B35b
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IDT72V3623
Abstract: IDT72V3653 IDT72V3663 IDT72V3673
Text: 3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36, 4,096 x 36, 8,192 x 36 FEATURES: ADVANCE INFORMATION IDT72V3653 IDT72V3663 IDT72V3673 ♦ ♦ Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
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IDT72V3653
IDT72V3663
IDT72V3673
128-pin
IDT723653/723663/723673
PK128-1)
72V3653
72V3663
72V3673
com/docs/PSC4045
IDT72V3623
IDT72V3653
IDT72V3663
IDT72V3673
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Untitled
Abstract: No abstract text available
Text: CMOS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 • • • FEATURES • • • • • • • Memory storage capacity: IDT723653 – 2,048 x 36 IDT723663 – 4,096 x 36 IDT723673 – 8,192 x 36 Clock frequencies up to 83 MHz 8 ns access time
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IDT723653
IDT723663
IDT723673
PK128-1)
drw25
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IC51-1324-828
Abstract: IDT723613 IDT72V3613
Text: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES: ♦ ♦ ♦ Passive parity checking on each Port Parity Generation can be selected for each Port Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)
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IDT72V3613
132-pin
120-pin
IDT723613
83MHz
PN120-1)
PQ132-1)
72V3613
com/docs/PSC4036
com/docs/PSC4021
IC51-1324-828
IDT723613
IDT72V3613
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Untitled
Abstract: No abstract text available
Text: CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36 FEATURES: • • • • • • • • • Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 Clocked FIFO buffering data from Port A to Port B Clock frequencies up to 83 MHz 8 ns access time
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IDT723623
IDT723633
IDT723643
PK128-1)
drw22
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Untitled
Abstract: No abstract text available
Text: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • • FEATURES: • • • • • • • • • • • • • 64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 83MHz
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IDT72V3613
83MHz
PN120-1)
PQ132-1)
72V3613
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723674
Abstract: No abstract text available
Text: 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 • • • FEATURES • • • • • • • Memory storage capacity: IDT72V3654 – 2,048 x 36 x 2 IDT72V3664 – 4,096 x 36 x 2 IDT72V3674 – 8,192 x 36 x 2 Clock frequencies up to 100 MHz 6.5ns access time
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IDT72V3654
IDT72V3664
IDT72V3674
2V3674
drw36
723674
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Untitled
Abstract: No abstract text available
Text: SFT501 and SFT503 Series Solid State Devices, Inc. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 [email protected] * www.ssdi-power.com DESIGNER’S DATA SHEET 5 AMP 200 Volts HIGH SPEED PNP Transistor Part Number / Ordering Information 1/
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SFT501
SFT503
SFT502
SFT504
SFT501
SFT503
MIL-PRF-19500
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Untitled
Abstract: No abstract text available
Text: SFT502 and SFT504 Series Solid State Devices, Inc. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 [email protected] * www.ssdi-power.com DESIGNER’S DATA SHEET 5 AMP 200 Volts HIGH SPEED NPN Transistor Part Number / Ordering Information 1/
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PDF
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SFT502
SFT504
SFT501
SFT503
SFT502
SFT504
MIL-PRF-19500
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Untitled
Abstract: No abstract text available
Text: CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2 FEATURES: • • • • • • • • • Memory storage capacity: IDT723626 – 256 x 36 x 2 IDT723636 – 512 x 36 x 2 IDT723646 – 1,024 x 36 x 2 Clock frequencies up to 83 MHz 8ns access time
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IDT723626
IDT723636
IDT723646
36-bit
18-bit
18-bit
com/docs/PSC4045
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Untitled
Abstract: No abstract text available
Text: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings
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024x36x2
IDT72V3624
IDT72V3634
IDT72V3644
128-pin
T723624/723634/723644
PK128-1)
72V3624
72V3634
72V3644
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Untitled
Abstract: No abstract text available
Text: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A
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IDT723613
64x36
36-bits
18-bits
00S742b
IDT723613
PN120-1)
PQ132-1)
3145drw21
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Untitled
Abstract: No abstract text available
Text: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have
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PDF
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1024x36x2
IDT723626
IDT723636
IDT723646
18-bit
18-bits
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Untitled
Abstract: No abstract text available
Text: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted
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IDT723614
36-bits
18-bits
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Untitled
Abstract: No abstract text available
Text: 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • Passive parity checking on each Port • Parity Generation can be selected for each Port • Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)
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OCR Scan
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PDF
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132-pin
120-pin
IDT723613
IDT72V3613
83MHz
com/docs/PSC4036
com/docs/PSC4021
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Untitled
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.
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PDF
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256x36x2,
512x36x2,
024x36x2
IDT723624
IDT723634
IDT723644
2S771
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Untitled
Abstract: No abstract text available
Text: |dy Integrated Dev ice Technology, Inc. CMOS Triple Bus SyncFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY I D T y iii ll IDT723646 FEATURES: • Memory storage capacity: IDT723626-256 x 36 x 2 IDT723636-512 x 3 6 x 2 IDT723646-10 2 4 x 3 6 x 2
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PDF
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1024x36x2
IDT723646
IDT723626-256
IDT723636-512
IDT723646-10
36-bit
18-bit
IDT723626/723636/723646
PK128-1)
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Untitled
Abstract: No abstract text available
Text: Integrated Device TechnoJogy, lie. PRELIMINARY IDT723624 IDT723634 IDT723644 CMOS Sync BiFlFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.
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PDF
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IDT723624
IDT723634
IDT723644
1024x36x2
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pdic cd
Abstract: No abstract text available
Text: SN74ABT361 3 64 x 36 C L O C K E D F I R ST - I N, F I R S T - O U T M E M O R Y WITH BUS M A T C H IN G AND BYTE S W A P P I N G SC B S 128E -JU LY 1 9 9 2 - REVISED FEBRUARY 1996 F r e e - R u n n i n g C L K A and C L K B Can Be M i c r o p r o c e s s o r I nt er fac e Co nt rol Logic
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SN74ABT361
pdic cd
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CHN 044 VW
Abstract: NB18
Text: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 IDT723624 IDT723634 IDT723644 • Port B bus sizing ot 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian tormat tor word and byte bus sizes • Master Reset clears data and contigures FIFO, Partial
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PDF
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IDT723624-256
IDT723634-512
IDT723644-1
IDT723624
IDT723634
IDT723644
36-bits
18-bits
PK128-1
CHN 044 VW
NB18
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Untitled
Abstract: No abstract text available
Text: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 2 5 6 x 3 6 x 2, 512 x 3 6 x 2, 1,024 x 36 x 2_ FEATURES: • Memory storage capacity: IDT72V3624-256 x 36 x 2 IDT72V3634-512 x 36 x 2 IDT72V3644-1,024x36x2 • Clock frequencies up to 83 MHz 8ns access time
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PDF
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IDT72V3624-256
IDT72V3634-512
IDT72V3644-1
024x36x2
PK128-1)
72V3624
72V3634
72V3644
com/docs/PSC4045
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