CY62143BVLL-70BAI
Abstract: No abstract text available
Text: 47V CY62143BV MoBL PRELIMINARY 256K x 16 Static RAM Features • Low voltage range: — CY62143BV: 2.7V–3.6V • Ultra-low active, standby power • Automatic power-down when deselected • TTL Compatible inputs and outputs • CMOS for optimum speed/power
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CY62143BV
CY62143BV:
CY62143BVLL-70BAI
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Untitled
Abstract: No abstract text available
Text: CY14U256LA 256-Kbit 32 K x 8 nvSRAM 256-Kbit (32 K × 8) nvSRAM Features Functional Description • 35 ns access time ■ Internally organized as 32 K × 8 ■ Hands off automatic STORE on power down with only a small capacitor ■ STORE to QuantumTrap nonvolatile elements initiated by
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CY14U256LA
256-Kbit
CY14U256LA
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ultra fine pitch BGA
Abstract: CY62147CV25 CY62147CV30 CY62147CV33 CY62147V
Text: 47V CY62147CV25/30/33 MoBL 256K x 16 Static RAM Features cantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH or both BLE and BHE are HIGH . The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are
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CY62147CV25/30/33
I/O15)
CY62147CV25:
CY62147CV30:
CY62147CV33:
CY62147V
CY62147CV25/30/33
ultra fine pitch BGA
CY62147CV25
CY62147CV30
CY62147CV33
CY62147V
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Untitled
Abstract: No abstract text available
Text: CY62147CV25/30/33 ADVANCE INFORMATION MoBL 256K x 16 Static RAM are placed in a high-impedance state when: deselected CE HIGH , outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).
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CY62147CV25/30/33
CY62147CV25:
CY62147CV30:
CY62147CV33:
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CY7C1041DV33-10ZSXI
Abstract: CY7C1041DV33 CY7C1041DV33-10VXI
Text: CY7C1041DV33 PRELIMINARY 4-Mbit 256K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A17). If Byte
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CY7C1041DV33
CY7C1041CV33
48-ball
44-lead
400-mil)
44-pin
CY7C1041DV33-10ZSXI
CY7C1041DV33
CY7C1041DV33-10VXI
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Untitled
Abstract: No abstract text available
Text: CY14V104LA CY14V104NA 4-Mbit 512 K x 8 / 256 K × 16 nvSRAM 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16 (CY14V104NA) ■ Hands off automatic STORE on power-down with only a small
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CY14V104LA
CY14V104NA
CY14V104LA/CY14V104NA
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1041C 8 pin
Abstract: CY7C1041CV33-10BAI 1041C CY7C1041BV33 CY7C1041CV33
Text: CY7C1041CV33 256K x 16 Static RAM Features Byte HIGH Enable BHE is LOW, then data from I/O pins (I/O8 – I/O15) is written into the location specified on the address pins (A0 – A17). • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power
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CY7C1041CV33
I/O15)
CY7C1041BV33
CY7C1041CV33
CY7C1042CV33
1041C 8 pin
CY7C1041CV33-10BAI
1041C
CY7C1041BV33
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CY62146VLL-70ZI
Abstract: CY62146V
Text: 1*CY62146V MoBL CY62146V MoBL™ 256K x 16 Static RAM Features • Low voltage range: — CY62146V: 2.7V–3.6V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected
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CY62146V
CY62146V
CY62146V:
CY62146VLL-70ZI
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Untitled
Abstract: No abstract text available
Text: CY14V101LA CY14V101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Functional Description Features • 25 ns and 45 ns access times ■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) ■ Hands off automatic STORE on power down with only a small
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CY14V101LA
CY14V101NA
CY14V101LA)
CY14V101NA)
48-ball
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K6X0808C1D-BF55
Abstract: HY6264P AS6C1008-55SIN samsung p28 K6R4016V1D-UC10 as6c4008-55sin HYNIX IS61LV25616AL-10KLI GS71116AGP-10 uPD431000ACZ-70L
Text: cross_reference Density Organization Alliance Alliance Part Number Alliance Package Alliance Speed Samsung Samsung Part Number Cypress Cypress Part Number Cypress Package Cypress Package Code Cypress Speed IDT Part Number IDT Package IDT Package Code IDT Speed ISSI
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CY7C128A-15VC
CY7C128A-15SC
CY7C167A-15PC
CY7C168A-15PC
24PIN
20PIN
300MIL
K6X0808C1D-BF55
HY6264P
AS6C1008-55SIN
samsung p28
K6R4016V1D-UC10
as6c4008-55sin
HYNIX
IS61LV25616AL-10KLI
GS71116AGP-10
uPD431000ACZ-70L
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CY62146CV18
Abstract: No abstract text available
Text: CY62146CV18 MoBL2 256K x 16 Static RAM Features • High Speed — 55 ns and 70 ns availability • Low voltage range: — 1.65V–1.95V • Pin Compatible with CY62146BV18 • Ultra-low active power — Typical Active Current: 0.5 mA @ f = 1 MHz • •
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CY62146CV18
CY62146BV18
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CY62146CV18
Abstract: No abstract text available
Text: CY62146CV18 MoBL2 256K x 16 Static RAM Features • High Speed — 55 ns and 70 ns availability • Low voltage range: — 1.65V–1.95V • Pin Compatible with CY62146BV18 • Ultra-low active power — Typical Active Current: 0.5 mA @ f = 1 MHz • •
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CY62146CV18
CY62146BV18
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CY62147V
Abstract: CY62147VLL-70ZI
Text: 47V CY62147V MoBL 256K x 16 Static RAM Features • Low voltage range: — CY62147V: 2.7V–3.6V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected
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CY62147V
CY62147V:
CY62147VLL-70ZI
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CY62146CV30
Abstract: CY62146V
Text: CY62146CV30 MoBL 256K x 16 Static RAM Features reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 99% when deselected CE HIGH . The input/output pins (I/O0 – I/O15) are placed in a
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CY62146CV30
I/O15)
CY62146CV30:
CY62146V
CY62146V
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Untitled
Abstract: No abstract text available
Text: 147V CY62147CV25/30/33 MoBL 256K x 16 Static RAM Features cantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH or both BLE and BHE are HIGH . The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are
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CY62147CV25/30/33
I/O15)
CY62147CV25:
CY62147CV30:
CY62147CV33:
CY62147V
CY62147CV25/30/33
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CY62147CV18
Abstract: No abstract text available
Text: CY62147CV18 MoBL2 256K x 16 Static RAM Features power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH or both BLE and BHE are HIGH . The input/output pins (I/O0 through I/O15) are placed in a high-impedance
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CY62147CV18
I/O15)
CY62147CV18:
CY62147V18/BV18
BV48A.
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CY62146CV18
Abstract: No abstract text available
Text: CY62146CV18 MoBL2 256K x 16 Static RAM Features an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH . The input/output pins (I/O0 through I/O15) are
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CY62146CV18
I/O15)
CY62146CV18:
CY62146V18/BV18
CY62146BV18
CY62146CV18
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BA36B
Abstract: fBGA 80 package
Text: Package Diagrams Ball Grid Array Packages 36-Ball Thin BGA BA36A 51-85099-B 1 Package Diagrams 36-Ball 7.00 mm x 8.5 mm x 1.2 mm Thin BGA BA36B 51-85105-*C 2 Package Diagrams 42-Ball FBGA (7.0 x 5.0 x 1.2 mm) BA42 51-85139-*C 3 Package Diagrams 48-Ball (8.0 x 14.0 x 1.1 mm) Thin BGA BA47
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36-Ball
BA36A
51-85099-B
36-Ball
BA36B
42-Ball
48-Ball
BA48A
51-85096-D
BA36B
fBGA 80 package
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CY62146VLL-70BAI
Abstract: CY62146V CY62146VLL-70ZI
Text: 46V CY62146V MoBL 256K x 16 Static RAM Features • Low voltage range: — CY62146V: 2.7V–3.6V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected
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CY62146V
CY62146V:
CY62146VLL-70BAI
CY62146VLL-70ZI
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Untitled
Abstract: No abstract text available
Text: 47V CY62147CV18 MoBL2TM 256K x 16 Static RAM Features deselected CE HIGH or when CE is LOW and both BLE and BHE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are
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CY62147CV18
CY62147CV18:
CY6147V18/BV18
I/O15)
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Untitled
Abstract: No abstract text available
Text: CY14V104LA CY14V104NA 4-Mbit 512 K x 8 / 256 K × 16 nvSRAM 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16 (CY14V104NA) ■ Hands off automatic STORE on power-down with only a small
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CY14V104LA
CY14V104NA
CY14V104LA)
CY14V104NA)
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CY62146CV30
Abstract: CY62146V
Text: CY62146CV30 MoBL 256K x 16 Static RAM Features power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 99% when deselected CE HIGH . The input/output pins (I/O0–I/O15) are placed in a high-impedance
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CY62146CV30
I/O15)
CY62146CV30:
CY62146V
CY62146V
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CY7C1041BV33
Abstract: CY7C1041CV33 CY7C1041CV33-10BAC
Text: CY7C1041CV33 256K x 16 Static RAM Features HIGH Enable BHE is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power
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CY7C1041CV33
I/O15)
CY7C1041BV33
CY7C1041CV33
CY7C1042CV33
20-ns
CY7C1041BV33
CY7C1041CV33-10BAC
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CY62146CV30
Abstract: CY62146V
Text: CY62146CV30 MoBL 256K x 16 Static RAM Features power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by 99% when deselected CE HIGH . The input/output pins (I/O0–I/O15) are placed in a high-impedance
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CY62146CV30
I/O15)
CY62146CV30:
CY62146V
CY62146V
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