CY7C1316BV18
Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18
Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
18-Mbit
250-MHz
CY7C1316BV18
CY7C1318BV18
CY7C1320BV18
CY7C1916BV18
|
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18
Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses
|
Original
|
PDF
|
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit
CY7C1310BV18,
CY7C1910BV18,
CY7C1312BV18,
CY7C1314BV18
CY7C1310BV18
CY7C1312BV18
CY7C1910BV18
|
CY7C1311BV18
Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
18-Mbit
300-MHz
CY7C1311BV18
CY7C1313BV18
CY7C1315BV18
CY7C1911BV18
|
CY7C1416AV18
Abstract: CY7C1418AV18 CY7C1420AV18 CY7C1427AV18
Text: CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
36-Mbit
250-MHz
CY7C1416AV18
CY7C1418AV18
CY7C1420AV18
CY7C1427AV18
|
78 ball fbga thermal resistance
Abstract: No abstract text available
Text: CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1411AV18
CY7C1413AV18
CY7C1415AV18
36-Mbit
300-MHz
CY7C1426AV18
78 ball fbga thermal resistance
|
Untitled
Abstract: No abstract text available
Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces
|
Original
|
PDF
|
CY7C1393BV18
CY7C1394BV18
CY7C1393BV18,
CY7C1394BV18
|
Untitled
Abstract: No abstract text available
Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
18-Mbit
300-MHz
|
Untitled
Abstract: No abstract text available
Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
18-Mbit
300-MHz
|
Untitled
Abstract: No abstract text available
Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit
250-MHz
|
Untitled
Abstract: No abstract text available
Text: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM
|
Original
|
PDF
|
CY7C1317BV18
CY7C1319BV18
CY7C1321BV18
18-Mbit
300-MHz
600MHz)
CY7C1917BV18
BB165E
|
Untitled
Abstract: No abstract text available
Text: CY7C1422AV18 CY7C1423AV18 CY7C1424AV18 PRELIMINARY 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1422AV18
CY7C1423AV18
CY7C1424AV18
36-Mbit
300-MHz
600MHz)
CY7C1429AV18
|
Untitled
Abstract: No abstract text available
Text: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions
|
Original
|
PDF
|
CY7C1311BV18,
CY7C1911BV18
CY7C1313BV18,
CY7C1315BV18
18-Mbit
CY7C1911BV18,
CY7C1315BV18
|
CY7C1312BV18
Abstract: CY7C1314BV18 CY7C1312
Text: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses
|
Original
|
PDF
|
CY7C1312BV18
CY7C1314BV18
CY7C1312BV18
CY7C1314BV18
CY7C1312
|
CY7C1311BV18
Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
18-Mbit
300-MHz
CY7C1311BV18
CY7C1313BV18
CY7C1315BV18
CY7C1911BV18
|
|
Untitled
Abstract: No abstract text available
Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces
|
Original
|
PDF
|
CY7C1393BV18
CY7C1394BV18
CY7C1393BV18,
CY7C1394BV18
|
CY7C1312BV18-167BZC
Abstract: No abstract text available
Text: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1312BV18
CY7C1314BV18
18-Mbit
CY7C1312BV18,
CY7C1314BV18
CY7C1312BV18-167BZC
|
Untitled
Abstract: No abstract text available
Text: CY7C1510V18 CY7C1512V18 CY7C1514V18 PRELIMINARY 72-Mbit QDR-II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 2-Word Burst on all accesses
|
Original
|
PDF
|
CY7C1510V18
CY7C1512V18
CY7C1514V18
72-Mbit
300-MHz
SynchronY7C1525V18
300Mhz
VSS/144M
VSS/288M
300Mhz,
|
CY7C1393BV18-167BZC
Abstract: CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18
Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 PRELIMINARY 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18,512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
18-Mbit
250-MHz
CY7C1393BV18-167BZC
CY7C1392BV18
CY7C1393BV18
CY7C1394BV18
CY7C1992BV18
|
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18
Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit
250-MHz
CY7C1310BV18
CY7C1312BV18
CY7C1314BV18
CY7C1910BV18
|
CY7C1413V18
Abstract: CY7C1415AV18 CY7C1415V18
Text: CY7C1411V18 CY7C1426V18 CY7C1413V18 CY7C1415V18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1411V18
CY7C1426V18
CY7C1413V18
CY7C1415V18
36-Mbit
250-MHz
CY7C1413V18
CY7C1415AV18
CY7C1415V18
|
CY7C1317BV18
Abstract: CY7C1319BV18 CY7C1321BV18 CY7C1917BV18
Text: CY7C1317BV18 CY7C1917BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM
|
Original
|
PDF
|
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
18-Mbit
CY7C1317BV18,
CY7C1917BV18,
CY7C1319BV18,
CY7C1321BV18
CY7C1317BV18
CY7C1319BV18
CY7C1917BV18
|
FBGA PACKAGE thermal resistance
Abstract: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 CY7C1917BV18
Text: CY7C1317BV18 CY7C1917BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency
|
Original
|
PDF
|
CY7C1317BV18
CY7C1917BV18
CY7C1319BV18
CY7C1321BV18
18-Mbit
250-MHz
FBGA PACKAGE thermal resistance
CY7C1317BV18
CY7C1319BV18
CY7C1321BV18
CY7C1917BV18
|
CY7C1310BV18
Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port
Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
|
Original
|
PDF
|
CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
18-Mbit
CY7C1310BV18,
CY7C1910BV18,
CY7C1312BV18,
CY7C1314BV18
CY7C1310BV18
CY7C1312BV18
CY7C1910BV18
static SRAM single port
|
CY7C1413V18
Abstract: CY7C1415AV18 CY7C1415V18
Text: CY7C1411V18 CY7C1426V18 CY7C1413V18 CY7C1415V18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth
|
Original
|
PDF
|
CY7C1411V18
CY7C1426V18
CY7C1413V18
CY7C1415V18
36-Mbit
250-MHz
CY7C1413V18
CY7C1415AV18
CY7C1415V18
|