LH Research
Abstract: GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
Text: EDI2AG27264V 1 Megabyte Sync/Sync Burst, Small Outline DIMM ADVANCED Advanced 2x64Kx72, 3.3V Sync/Sync Burst Flow-Through Module Features • 2x64Kx72 Synchronous, Synchronous Burst • Flow-Through Architecture • Linear Burst MODE • Clock Controlled Registered Bank
|
Original
|
EDI2AG27264V
2x64Kx72,
2x64Kx72
EDI2AG27264VxxD1
Module64Kx72
2x64Kx72
01581USA
EDI2AG27264V
LH Research
GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
|
PDF
|
MT41LC256K32D4
Abstract: BEDO RAM MT4C16270 Matsushita fp-m MT4LC4M4G6 MT4C1004J MT4C16257 MT4C4001J MT4LC1M16C3 MT4LC1M16E5
Text: TM Burst EDO DRAMs TECHNOLOGY, INC. 1 What are Burst EDO DRAMs? Burst EDO BEDO DRAMs are the Best Solution for 66 MHz Systems ❏ Standard DRAMs with shorter page mode cycle times ❏ EDO DRAMs that contain a pipeline stage and a 2-bit burst counter ❏
|
Original
|
|
PDF
|
M200
Abstract: W25P010A 32KX32
Text: /* * * File Name: w25p010a.v * Product: W25P010A * Features: 32k x 32 burst pipelined SRAM * * access time: 6ns pipelined data output capability * 2T/2T mode Signal cycle desllected mode * * Intel burst mode & linear burst mode selection LBO
|
Original
|
w25p010a
W25P010A
32kx32
M200
|
PDF
|
104 white noise
Abstract: WED2DG472512V-D2
Text: White Electronic Designs WED2DG472512V-D2 ADVANCED* 16MB 4x512Kx72 SYNC BURST-PIPELINE, DUAL KEY DIMM DESCRIPTION FEATURES 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin
|
Original
|
WED2DG472512V-D2
4x512Kx72)
WED2DG472512V
4x512Kx72.
14mmx20mm
WED2DG472512V5D2
200MHz
WED2DG472512V6D2
166MHz
WED2DG472512V65D2
104 white noise
WED2DG472512V-D2
|
PDF
|
EDI2AG272128V-D1
Abstract: GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
Text: White Electronic Designs EDI2AG272128V-D1 ADVANCED* 2 Megabyte Sync/Sync Burst, Small Outline DIMM FEATURES 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear Burst Mode Clock Controlled Registered Bank Enables E1#, E2#
|
Original
|
EDI2AG272128V-D1
2x128Kx72
EDI2AG272128VxxD1
2x128Kx72.
14mmx20mm
EDI2AG272128V85D1*
4x256Kx72
EDI2AG272128V9D1*
EDI2AG272128V10D1
EDI2AG272128V-D1
GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: White Electronic Designs WED2CG472512V-D2 ADVANCED* 16MB 4x512Kx72 SYNC / SYNC BURST, DUAL KEY DIMM SRAM MODULE DESCRIPTION FEATURES n 4x512Kx72 Synchronous, Synchronous Burst n Flow-Through Architecture n Linear and Sequential Burst Support via MODE pin
|
Original
|
4x512Kx72)
4x512Kx72
50MHz
WED2CG472512V-D2
WED2CG472512V9D2
WED2CG472512V10D2
WED2CG472512V12D2
WED2CG472512V15D2
|
PDF
|
Untitled
Abstract: No abstract text available
Text: White Electronic Designs WED2DG472512V-D2 ADVANCED* 16MB 4x512Kx72 SYNC BURST-PIPELINE, DUAL KEY DIMM DESCRIPTION FEATURES n 4x512Kx72 Synchronous, Synchronous Burst n Pipeline Architecture; Single Cycle Deselect n Linear and Sequential Burst Support via MODE pin
|
Original
|
WED2DG472512V-D2
4x512Kx72)
4x512Kx72
WED2DG472512V5D2
WED2DG472512V6D2
WED2DG472512V65D2
WED2DG472512V7D2
200MHz
166MHz
150MHz
|
PDF
|
EDI2AG272129V
Abstract: GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
Text: White Electronic Designs EDI2AG272129V ADVANCED* 2 Megabyte Sync/Sync Burst, Small Outline DIMM DESCRIPTION FEATURES 2x128Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Sequential Burst MODE Clock Controlled Registered Bank Enables E1#, E2#
|
Original
|
EDI2AG272129V
2x128Kx72
EDI2AG272129VxxD1
2x128Kx72.
14mmx20mm
EDI2AG272129V85D1*
2x128Kx72
EDI2AG272129V9D1*
EDI2AG272129V10D1
EDI2AG272129V
GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: EDI2CG27264V 1 Megabyte Sync/Sync Burst, Small Outline DIMM FEATURES • 2x64Kx72 Synchronous, Synchronous Burst • Flow-Through Architecture • Linear and Sequential Burst Support via MODE pin • Clock Controlled Registered Bank Enables E1\, E2\ •
|
Original
|
EDI2CG27264V
EDI2CG27264VxxD2
2CG27264V
EDI2CG27264V85D1*
EDI2CG27264V9D1*
EDI2CG27264V10D1
EDI2CG27264V12D1
2x64Kx72
|
PDF
|
GS8320E18T-133
Abstract: GS8320E18T-150 GS8320E18T-166 GS8320E18T-200 GS8320E18T-225 GS8320E18T-250 GS8320E32T-150 GS8320E32T-166 GS8320E32T-200 GS8320E32T-225
Text: Preliminary GS8320E18/32/36T-xxxV 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address
|
Original
|
GS8320E18/32/36T-xxxV
100-Pin
8320EV18
8320Exx
GS8320E18T-133
GS8320E18T-150
GS8320E18T-166
GS8320E18T-200
GS8320E18T-225
GS8320E18T-250
GS8320E32T-150
GS8320E32T-166
GS8320E32T-200
GS8320E32T-225
|
PDF
|
DT38
Abstract: 1995 SDRAM
Text: TN-04-38 WHAT IS BURST EDO? TECHNOLOGY, INC. TECHNICAL NOTE WHAT IS BURST EDO? INTRODUCTION Burst Extended Data-Out BEDO or pipeline nibble mode (as it has been termed by JEDEC), is basically an EDO DRAM that contains a pipeline stage and a 2-bit burst counter. This evolutionary approach to a high-speed DRAM
|
Original
|
TN-04-38
DT38
1995 SDRAM
|
PDF
|
marking A00
Abstract: 71128 GVT71128D18
Text: GALVANTECH, INC. GVT71128D18 128K X 18 SYNCHRONOUS BURST SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT 128K x 18 SRAM +3.3V POWER SUPPLY, FULLY REGISTERED, BURST COUNTER FEATURES GENERAL DESCRIPTION • • • • • The Galvantech Synchronous Burst SRAM family
|
Original
|
GVT71128D18
GVT71128D18
072x18
71128D18
marking A00
71128
|
PDF
|
burst SRAM
Abstract: EDI2CG272128V GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
Text: EDI2CG272128V 2x128Kx72, 3.3V Sync/Sync Burst Flow-Through FEATURES • 2x128Kx72 Synchronous, Synchronous Burst The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM 144 contacts Module, small outline. The Module contains four (4) Synchronous Burst Ram Devices,
|
Original
|
EDI2CG272128V
2x128Kx72,
2x128Kx72
EDI2CG272128VxxD1
14mmx20mm
EDI2CG272128V85D1*
EDI2CG272128V9D1*
EDI2CG272128V12D1
EDI2CG272128V15D1
2x128Kx72
burst SRAM
EDI2CG272128V
GW CSSRM1.PC-MFNQ-5C7E-1-700-R18
|
PDF
|
GVT71128B18
Abstract: No abstract text available
Text: PRELIMINARY GALVANTECH, INC. GVT71128B18 128K X 18 SYNCHRONOUS BURST SRAM 128K x 18 SRAM SYNCHRONOUS BURST SRAM +3.3V POWER SUPPLY , REGISTERED INPUTS, BURST COUNTER FEATURES GENERAL DESCRIPTION • • • • • • The Galvantech Synchronous Burst SRAM family
|
Original
|
GVT71128B18
GVT71128B18
072x18
71128B18
access/10ns
access/11ns
access/15ns
|
PDF
|
|
EDI2CG472256V
Abstract: No abstract text available
Text: White Electronic Designs EDI2CG472256V ADVANCED* 8 Megabyte Sync/Sync Burst, Dual Key DIMM FEATURES 4x256Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable EM#
|
Original
|
EDI2CG472256V
4x256Kx72
EDI2CG472256VxxD2
4x256Kx72.
14mmx20mm
EDI2CG472256V9D2*
4x256Kx72
EDI2CG472256V10D2*
EDI2CG472256V12D2
EDI2CG472256V
|
PDF
|
GVT71128D32
Abstract: No abstract text available
Text: GALVANTECH, GVT71128D32 128K X 32 SYNCHRONOUS BURST SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT 128K x 32 SRAM +3.3V SUPPLY, PIPELINED, SINGLE CYCLE DESELECT, BURST COUNTER FEATURES GENERAL DESCRIPTION • • • • • The Galvantech Synchronous Burst SRAM family
|
Original
|
GVT71128D32
GVT71128D32
072x32
71128D32
access/10ns
access/12ns
access/15ns
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ^EDI EEH2AG27265V 1Megabyte Sync/Sync Burst, ^ ^ ^ ^ S m a ll Outline DIMM •ELECTRONIC DESI SMS, INC ADVANCED 2x64Kx72, 3.3V Module Features Sync/Sync Burst Flow-Through • 2x64kx72 Synchronous, Synchronous Burst ■ Flow-Through Architecture • Sequential Burst MODE
|
OCR Scan
|
EEH2AG27265V
2x64Kx72,
EDI2AG27265VxxD1
2x64Kx72.
JEDEC14mmx20mmTQFP
ay265V
265V85D1
EDI2AG27265V9D1
EDI2AG27265V1
EDI2AG272G5V12D1
|
PDF
|
Untitled
Abstract: No abstract text available
Text: m EDI2CG27264V 1 Megabyte Sync/Sync Burst, Small Outline DIMM \ ELECTRONIC DESIGNS. IN C ADVANCED 2x128Kx72, 3.3V Module Features Sync/Sync Burst Flow-Through • 2x128K x72 Synchronous, S ynchronous Burst • Flow-Through A rchitecture • Linear and Sequential Burst Support via MODE pin
|
OCR Scan
|
EDI2CG27264V
2x128Kx72
2x128Kx72,
EDI2CG27264V85D1
2x64Kx72
EDI2CG27264V9D1*
EDI2CG27264V10D1
EDI2CG27264V12D1
|
PDF
|
617-2240
Abstract: 273505 OJ-11
Text: Advanced Micro Devices Am27 HB010 1 Megabit 131,072 x 8-Bit Burst Mode CMOS EPROM DISTINCTIVE CHARACTERISTICS • Highspeed - 50 ns random access - 15 ns burst access ■ No burst boundary ■ No burst limit ■ Pin compatible with Am27C010 Supports all “Burst" microprocessors
|
OCR Scan
|
Am27HB010
Am27C010
Am29000
WCP-13
5M-1/92-0
617-2240
273505
OJ-11
|
PDF
|
EDI2CG472128V
Abstract: No abstract text available
Text: EDI2CG472128V 4 Megabyte Sync/Sync Burst, Dual Key DIMM Advanced 4x128Kx72, 3.3 V Sync/Sync Burst Flow-Through • 4x128K x72 Synchronous, S ynchronous Burst • Flow-Through A rchitecture • Linear and Sequential Burst Support via MODE pin DIMM 168 contacts Module, organized as 4x128Kx72.
|
OCR Scan
|
EDI2CG472128V
4x128Kx72
CG472128V15D2
050TVP.
EDI2CG472128V
|
PDF
|
am27c0
Abstract: AM27C010 12416B CLI10
Text: Cl Advanced Micro Devices A m 2 7 H B 0 1 0 1 Megabit 131,072 x 8-Bit Burst Mode CMOS EPROM DISTINCTIVE CHARACTERISTICS • High speed - 50 ns random access - 15 ns burst access ■ No burst boundary ■ No burst limit ■ Pin compatible with Am27C010 Supports all “Burst” microprocessors
|
OCR Scan
|
Am27HB010
Am27C010
Am29000
WCP-13
5M-1/92-0
am27c0
12416B
CLI10
|
PDF
|
KMM764V41AG2-15
Abstract: 15SRAM KMM76 kmm764v41
Text: KMM764V41AG2 SRAM MODULE 256KB Synchronous Pipelined Burst SRAM Module PIN CONFIGURATION Top View FEATURES Implemented based on COAST 3.1 Supports Interleave Burst and Linear Burst Mode Zero-wait-state operation at 75/66MHz TTL compatible inputs/outputs
|
OCR Scan
|
KMM764V41AG2
256KB
75/66MHz
160-pin
1130mil)
KMM764V41AG2-13/15
KMM764V41AG2-15
15SRAM
KMM76
kmm764v41
|
PDF
|
Untitled
Abstract: No abstract text available
Text: EDI2CG472256V_ 8 Megabyte Sync/Sync Burst, Dual Key DIMM FEATURES 4x256Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable EM\ Clock Controlled Registered Bank Enables (E1\,
|
OCR Scan
|
EDI2CG472256V_
4x256Kx72
EDI2CG472256V
4x256K
472256V12D
472256V15D
|
PDF
|
KMM764V41AG7-15
Abstract: AL3A u58 136 kmm764v41
Text: KMM764V41AG7 SRAM MODULE 256KB Synchronous Pipelined Burst SRAM Module PIN CONFIGURATION Top View FEATURES Implemented based on COAST 3.1 Supports Interleave Burst and Linear Burst Mode Zero-wait-state operation at 75/66MHz TTL compatible inputs/outputs
|
OCR Scan
|
KMM764V41AG7
256KB
75/66MHz
160-pin
KMM764V41AG7-13/15
36Address
KMM764V41AG7-15
AL3A
u58 136
kmm764v41
|
PDF
|