MIL-STD-1835
Abstract: D22 PACKAGE DIAGRAM 40 PIN CERDIP D2 Package diagram D2 Package MIL-STD d 1835 D5011 cerdip cerdip 16 lead
Text: Package Diagram Ceramic Dual-In-Line Packages 16-Lead 300-Mil CerDIP D2 MIL-STD-1835 D-2 Config. A 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-6 Config. A 1 Package Diagram 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 22–Lead (400–Mil) CerDIP D8
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16-Lead
300-Mil)
MIL-STD-1835
18-Lead
20-Lead
D22 PACKAGE DIAGRAM
40 PIN CERDIP
D2 Package diagram
D2 Package
MIL-STD
d 1835
D5011
cerdip
cerdip 16 lead
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w32 transistor
Abstract: W32 Package transistor w16 W6 Diode MIL-STD-1835 cerdip CERDIP Package W6 Package D-10 600MIL
Text: Package Diagram Ceramic Windowed Dual-In-Line Packages 20-Lead 300-Mil Windowed CerDIP W6 MIL-STD-1835 D-8 Config. A 24-Lead (600-Mil) Windowed CerDIP W12 MIL-STD-1835 D-3 Config. A 1 Package Diagram 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A
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20-Lead
300-Mil)
MIL-STD-1835
24-Lead
600-Mil)
28-Lead
w32 transistor
W32 Package
transistor w16
W6 Diode
cerdip
CERDIP Package
W6 Package
D-10
600MIL
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80041
Abstract: MIL-STD-1835 40 PIN CERDIP cerdip D16 PACKAGE DIAGRAM 80046 CERDIP 52 D2 Package diagram D22 PACKAGE DIAGRAM D50 transistor
Text: Package Diagram Ceramic Dual-In-Line Packages 16-Lead 300-Mil CerDIP D2 MIL-STD-1835 D-2 Config. A 51-80027 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-6 Config. A 51-80028 1 Package Diagram 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 51-80029
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16-Lead
300-Mil)
MIL-STD-1835
18-Lead
20-Lead
22-Lead
80041
40 PIN CERDIP
cerdip
D16 PACKAGE DIAGRAM
80046
CERDIP 52
D2 Package diagram
D22 PACKAGE DIAGRAM
D50 transistor
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MIL-STD-1835
Abstract: D-10 1835
Text: Package Diagrams Ceramic Windowed Dual-In-Line Packages 20-Lead 300-Mil Windowed CerDIP W6 MIL-STD-1835 D-8 Config. A 24-Lead (600-Mil) Windowed CerDIP W12 MIL-STD-1835 D-3 Config. A 1 Package Diagrams 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A
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20-Lead
300-Mil)
MIL-STD-1835
24-Lead
600-Mil)
28-Lead
D-10
1835
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MIL-STD-1835
Abstract: sidebraze
Text: Package Diagrams Ceramic Dual-In-Line Packages 16-Lead 300-Mil CerDIP D2 MIL-STD-1835 D-2 Config. A 51-80027 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-6 Config. A 51-80028 1 Package Diagrams 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 51-80029
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16-Lead
300-Mil)
MIL-STD-1835
18-Lead
20-Lead
22-Lead
sidebraze
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 14 PIN CERAMIC DIP-14C-C04 EIAJ code : ∗DIP014-G-0300-4 Lead pitch 100mil Row spacing 300mil Sealing method Cerdip 14-pin ceramic DIP DIP-14C-C04 14-pin ceramic DIP (DIP-14C-C04) +0.71 19.30 –0.15 .760 +.028 –.006 R0.64(.025) REF
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DIP-14C-C04
DIP014-G-0300-4
100mil
300mil
14-pin
DIP-14C-C04)
D14006SC-2-3
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 18 PIN CERAMIC DIP-18C-C01 EIAJ code : ∗DIP018-G-0300-2 18-pin ceramic DIP Lead pitch 100mil Row spacing 300mil Sealing method Cerdip DIP-18C-C01 18-pin ceramic DIP (DIP-18C-C01) +0.56 22.61–0.20 +.022 .890 –.008 R0.64(.025) REF
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DIP-18C-C01
DIP018-G-0300-2
100mil
300mil
18-pin
DIP-18C-C01)
D18005SC-4-3
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 16 PIN CERAMIC DIP-16C-C01 EIAJ code : ∗DIP016-G-0300-2 Lead pitch 100mil Row spacing 300mil Sealing method Cerdip 16-pin ceramic DIP DIP-16C-C01 16-pin ceramic DIP (DIP-16C-C01) +0.71 19.30 –0.15 .760 +.028 –.006 R0.64(.025) REF
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DIP-16C-C01
DIP016-G-0300-2
100mil
300mil
16-pin
DIP-16C-C01)
D16011SC-2-3
Dimensi16
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 20 PIN CERAMIC DIP-20C-C01 EIAJ code : ∗DIP020-G-0300-1 20-pin ceramic DIP Lead pitch 100mil Row spacing 300mil Sealing method Cerdip DIP-20C-C01 20-pin ceramic DIP (DIP-20C-C01) +1.27 24.13 –0.25 +.050 .950 –.010 R0.64(.025) REF
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DIP-20C-C01
DIP020-G-0300-1
100mil
300mil
20-pin
DIP-20C-C01)
D20001SC-3-3
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 16 PIN CERAMIC DIP-16C-C04 EIAJ code : ∗DIP016-G-0300-5 Lead pitch 100mil Row spacing 300mil Sealing method Cerdip 16-pin ceramic DIP DIP-16C-C04 16-pin ceramic DIP (DIP-16C-C04) +0.71 19.30 –0.15 +.028 .760 –.006 R0.64(.025) REF
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DIP-16C-C04
DIP016-G-0300-5
100mil
300mil
16-pin
DIP-16C-C04)
D16032SC-4-3
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DIP-14C-C01
Abstract: D1400
Text: DUAL IN-LINE PACKAGE 14 PIN CERAMIC DIP-14C-C01 EIAJ code : ∗DIP014-G-0300-1 Lead pitch 100mil Row spacing 300mil Sealing method Cerdip 14-pin ceramic DIP DIP-14C-C01 14-pin ceramic DIP (DIP-14C-C01) +0.71 19.30 −0.15 +.028 .760 −.006 R0.64(.025) REF
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DIP-14C-C01
DIP014-G-0300-1
100mil
300mil
14-pin
DIP-14C-C01)
D14005SC-2-4
DIP-14C-C01
D1400
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Untitled
Abstract: No abstract text available
Text: DUAL IN-LINE PACKAGE 16 PIN CERAMIC DIP-16C-C02 EIAJ code : ∗DIP016-G-0300-3 Lead pitch 100mil Row spacing 300mil Sealing method Cerdip 16-pin ceramic DIP DIP-16C-C02 16-pin ceramic DIP (DIP-16C-C02) +0.71 19.30 –0.15 .760 +.028 –.006 R0.64(.025) REF
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DIP-16C-C02
DIP016-G-0300-3
100mil
300mil
16-pin
DIP-16C-C02)
D16012SC-3-3
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Untitled
Abstract: No abstract text available
Text: SKINNY DUAL IN-LINE PACKAGE 22 PIN CERAMIC DIP-22C-C03 EIAJ code : ∗DIP022-G-0300-1 22-pin ceramic SK-DIP Lead pitch 100mil Row spacing 300mil Sealing method Cerdip DIP-22C-C03 22-pin ceramic SK-DIP (DIP-22C-C03) +0.76 +.030 27.18 –0.26 1.070 –.010
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DIP-22C-C03
DIP022-G-0300-1
100mil
300mil
22-pin
DIP-22C-C03)
D22009SC-3-3
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CY27C256
Abstract: 27C256-70 27C256 27C256-200 27C256-45 27C256 UV 27C256-150 27c256120
Text: fax id: 3013 1CY 27C2 56 CY27C256 32K x 8-Bit CMOS EPROM Features able in a CerDIP package equipped with an erasure window to provide for reprogrammability. When exposed to UV light, the EPROM is erased and can be reprogrammed. The memory cells utilize proven EPROM floating gate technology and
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CY27C256
CY27C256
27C256-70
27C256
27C256-200
27C256-45
27C256 UV
27C256-150
27c256120
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cy7c271-35wmb
Abstract: 7C271 CY7C271-45WMB 7C274 CY7C271 CY7C274 cy7c271-35wm
Text: CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Features low-power stand-by mode. The CY7C271 is packaged in the 300-mil slim package. The CY7C274 is packaged in the industry standard 600-mil package. Both the CY7C271 and CY7C274 are available in a cerDIP package equipped with an
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CY7C271
CY7C274
CY7C271
300-mil
CY7C274
600-mil
cy7c271-35wmb
7C271
CY7C271-45WMB
7C274
cy7c271-35wm
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A14A0
Abstract: 7C271 7C274 CY7C271 CY7C274 CY7C271-45WMB
Text: 1CY7C274 CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM low-power stand-by mode. The CY7C271 is packaged in the 300-mil slim package. The CY7C274 is packaged in the industry standard 600-mil package. Both the CY7C271 and CY7C274 are available in a cerDIP package equipped with an
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1CY7C274
CY7C271
CY7C274
CY7C271
300-mil
CY7C274
600-mil
A14A0
7C271
7C274
CY7C271-45WMB
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CY7C271-35WMB
Abstract: 7C271 7C274 CY7C271 CY7C274
Text: CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Features low-power stand-by mode. The CY7C271 is packaged in the 300-mil slim package. The CY7C274 is packaged in the industry standard 600-mil package. Both the CY7C271 and CY7C274 are available in a cerDIP package equipped with an
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CY7C271
CY7C274
CY7C271
300-mil
CY7C274
600-mil
CY7C271-35WMB
7C271
7C274
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CY7B333
Abstract: No abstract text available
Text: I UOOO. O /O U /9 U Revision: Tuesday, December 22,1992 - CY7B333B PRELIMINARY CYPRESS " SEMICONDUCTOR General-Purpose Synchronous BiCMOS PLD • Available in 28-pin, 300-mil PDIP, cerDIP, PLCC, and LCC packages • Programmable security bit Features • 16 I/O macrocells, each having:
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CY7B333B
CY7B333
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Untitled
Abstract: No abstract text available
Text: CY7B339 PRELIMINARY CYPRESS SEMICONDUCTOR • Available in 28-pin 300-mil PDIP and CerDIP, and in SOJ, PLCC, and LCC packages • Very high performance decoder with latched outputs — tpD = 7 ns Functional Description The CY7B339 is a 7-ns, 28-pin program
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CY7B339
CY7B339
28-pin,
300-mil
28-pin
CY7B339--
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7B339
Abstract: 7B339-7
Text: CY7B339 PRELIMINARY CYPRESS SEMICONDUCTOR 7-ns BiCMOS PAL with Output Latches • Available in 28-pin 340-mil PDIP and CerDIP, and in SOJ, PLCC, and LCC packages Features • Very high performance decoder with latched outputs — tpo = 7 ns — tLEO = 5-5 ns
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CY7B339
28-pin
300-mil
CY7B339â
CY7B339
7B339
7B339-7
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Untitled
Abstract: No abstract text available
Text: fax id: 3016 CYPRESS PRELIMINARY CY7C271A 32K x 8 Power Switched and Reprogrammable matically powers down into a low-power stand-by mode. The CY7C271A is packaged in the 300-mil slim package and is available in a cerDIP package equipped with an erasure w in
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CY7C271A
CY7C271A
300-mil
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PALC22V10-30DMB
Abstract: PALC22V10L-25WC PALC22V10-25DMB PALC22V10 p10j PALC22V10-35PC 22V10-25 cypress PALC22V10 22V10-30 PALC22V10L35PC
Text: 4bE T> CYPRESS SEMICONDUCTOR 250=^5 OOQbTfciM 3 E K Y P PALC22V10 "“* cip R E S S SEMICONDUCTOR & 22 inputs and 10 outputs. When the win dowed cerDIP is exposed to UV light, the 22V10 is erased and can then be repro grammed. The programmable macrocell
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PALC22V10
PALC22V10L-35HC
PALC22V10L-35JC
PALC22V10L-35PC
PALC22V10L-35WC
PALC22V10-35HC
PALC22V10
PALC22V10-35PC/PI
PALC22V10-35WC/WI
PALC22V10-40DMB
PALC22V10-30DMB
PALC22V10L-25WC
PALC22V10-25DMB
p10j
PALC22V10-35PC
22V10-25
cypress PALC22V10
22V10-30
PALC22V10L35PC
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85C960
Abstract: D85C960-20 231369 d85c960-25 Erasable Programmable Logic Device 610 LSC5
Text: in te i 85C960 1-MICRON CHMOS 80960 K-SERIES BUS CONTROL juPLD Burst Logic, Ready Control, and Address Decode Support for 80960 KA/KB Embedded Controllers In Single Chip Operates with 80960KA/KB at 16 MHz, 20 MHz, and 25 MHz UV Erasable CerDIP or O T P tm
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85C960
80960KA/KB
28-Pin
300-mil
85C960
D85C960-20
231369
d85c960-25
Erasable Programmable Logic Device 610
LSC5
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7B338
Abstract: ic 7b338
Text: CY7B338 PRELIMINARY CYPRESS SEMICONDUCTOR • Available in 28>pin 300-mil PDIP and CerDIP, and in SOJ, PLCC, and LCC packages • Very high performance decoder with latched outputs — tpj — 6 ns Functional Description T he CY7B338 is a 6-ns, 28-pin p ro g ram
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CY7B338
7B338
CY7B338
7B338--7LMB
7B338--8VC
7B338--10DMB
7B338--10LMB
12DMB
ic 7b338
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