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    CY7C1311KV18 Price and Stock

    Infineon Technologies AG CY7C1311KV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1311KV18-250BZC Tray 680
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    • 1000 $22.72169
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    Avnet Americas CY7C1311KV18-250BZC Tray 680
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    Cypress Semiconductor CY7C1311KV18-250BZC

    SRAM Chip Sync Dual 1.8V 18M-bit 2M x 8 0.45ns 165-Pin FBGA Tray
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    Verical CY7C1311KV18-250BZC 136 13
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    • 100 $27.4875
    • 1000 $24.85
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    CY7C1311KV18-250BZC 125 13
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    Rochester Electronics CY7C1311KV18-250BZC 261 1
    • 1 $23.39
    • 10 $23.39
    • 100 $21.99
    • 1000 $19.88
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    CY7C1311KV18 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1311KV18-250BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA Original PDF

    CY7C1311KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1311KV18 – 2 M x 8 ■ 333-MHz clock for high bandwidth


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit CY7C1311KV18 333-MHz CY7C1313KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18 18-Mbit CY7C1311KV18 333-MHz CY7C1313KV18 CY7C1315KV18 PDF