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Rochester Electronics LLC CY7C1314BV18-200BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1314BV18-200BZC	Tray			9	1 - 10 $33.51 100 $33.51 1000 $33.51 10000 $33.51	Buy Now
Infineon Technologies AG CY7C1314BV18-200BZC IC SRAM 18MBIT PARALLEL 165FBGA
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DigiKey	CY7C1314BV18-200BZC	Tray			136	1 - 10 - 100 - 1000 $32.35007 10000 $32.35007	Buy Now
Rochester Electronics LLC CY7C1314BV18-250BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1314BV18-250BZC	Tray			9	1 - 10 $34.96 100 $34.96 1000 $34.96 10000 $34.96	Buy Now
Infineon Technologies AG CY7C1314BV18-250BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1314BV18-250BZC	Tray			136	1 - 10 - 100 - 1000 $33.65397 10000 $33.65397	Buy Now
Infineon Technologies AG CY7C1314BV18-167BZI IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1314BV18-167BZI	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now

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CY7C1314BV18 Datasheets (11)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1314BV18		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-167BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-167BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-167BZI		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA		Original	PDF
CY7C1314BV18-167BZXC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-200BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-200BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-200BZXC		Cypress Semiconductor	18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V		Original	PDF
CY7C1314BV18-250BZC		Cypress Semiconductor	18-Mbit QDR -II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-250BZC		Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture		Original	PDF
CY7C1314BV18-250BZXC		Cypress Semiconductor	18-Mbit QDR -II SRAM 2-Word Burst Architecture		Original	PDF

CY7C1314BV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz
CY7C1312BV18 Abstract: CY7C1314BV18 CY7C1312 Text: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses	Original	PDF	CY7C1312BV18 CY7C1314BV18 CY7C1312BV18 CY7C1314BV18 CY7C1312
CY7C1312BV18-167BZC Abstract: No abstract text available Text: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	PDF	CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1312BV18, CY7C1314BV18 CY7C1312BV18-167BZC
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 CY7C1910BV18
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18 static SRAM single port
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz
Untitled Abstract: No abstract text available Text: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	PDF	CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1312BV18, CY7C1314BV18
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1314BV18-167BZXI Text: CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	PDF	CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 18-Mbit CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1314BV18-167BZXI
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	PDF	CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 300-MHz CY7C1910BV18 BB165E BB165D
Xilinx spartan xc3s400_ft256 Abstract: XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256 Text: Memory Interface Solutions User Guide UG086 v3.3 December 2, 2009 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,	Original	PDF	UG086 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 Xilinx spartan xc3s400_ft256 XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	PDF	CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
burst sram 4000 Abstract: CY7C1314BV18 K7R323684M SRL16 UG070 XAPP703 xilinx mig user interface design Text: Application Note: Virtex-4 Family R QDR II SRAM Interface for Virtex-4 Devices Author: Derek Curd XAPP703 v2.4 July 9, 2008 Summary This application note describes the implementation and timing details of a 2-word or 4-word burst Quad Data Rate (QDR II) SRAM interface for Virtex -4 devices. The synthesizable	Original	PDF	XAPP703 burst sram 4000 CY7C1314BV18 K7R323684M SRL16 UG070 XAPP703 xilinx mig user interface design