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    CY7C1370B Price and Stock

    Rochester Electronics LLC CY7C1370B-150AC

    IC SRAM 18MBIT PAR 100TQFP
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    Rochester Electronics LLC CY7C1370B-133AC

    IC SRAM 18MBIT PARALLEL 100TQFP
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    Rochester Electronics LLC CY7C1370B-200AC

    IC SRAM 18MBIT PARALLEL 100TQFP
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    Rochester Electronics LLC CY7C1370B-133BGC

    IC SRAM 18MBIT PARALLEL 119PBGA
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    Rochester Electronics LLC CY7C1370B-200BGC

    IC SRAM 18MBIT PARALLEL 119PBGA
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    CY7C1370B Datasheets (8)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1370B Cypress Semiconductor 512K x 36/1M x 18 Pipelined SRAM with NoBLTM Architecture Original PDF
    CY7C1370B-133AC Cypress Semiconductor IC SRAM 18MBIT 133MHZ 100LQFP Original PDF
    CY7C1370B-133BGC Cypress Semiconductor IC SRAM 18MBIT 133MHZ 119BGA Original PDF
    CY7C1370B-200AC Cypress Semiconductor 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1370BV25 Cypress Semiconductor 512K x 36/1M x 18 Pipelined SRAM with NoBLTM Architecture Original PDF
    CY7C1370BV25-133AC Cypress Semiconductor IC SRAM 18MBIT 133MHZ 100LQFP Original PDF
    CY7C1370BV25-167AC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 100LQFP Original PDF
    CY7C1370BV25-200AC Cypress Semiconductor 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Original PDF

    CY7C1370B Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1370B

    Abstract: CY7C1372B
    Text: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1370B CY7C1372B 36/1M CY7C1370B/CY7C1372B 36/1M CY7C1370B CY7C1372B

    Untitled

    Abstract: No abstract text available
    Text: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1370B CY7C1372B 36/1M CY7C1370B/CY7C1372B 36/1M BG119) BB165A)

    CY7C1370BV25-167AC

    Abstract: CY7C1370BV25 CY7C1372BV25
    Text: CY7C1372BV25 CY7C1370BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200,167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1372BV25 CY7C1370BV25 36/1M CY7C1370BV25-167AC CY7C1370BV25 CY7C1372BV25

    CY7C1370B

    Abstract: CY7C1370B-133AC CY7C1372B
    Text: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1370B CY7C1372B 36/1M CY7C1370B/CY7C1372B 36/1M CY7C1370B CY7C1370B-133AC CY7C1372B

    TMS 3766

    Abstract: DPA 51 7C1370
    Text: 1CY7C1372BV25 CY7C1370BV25 CY7C1372BV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 180,166, 150, and 133 MHz • Fast access time: 3.0,3.2,3.4, 3.8, 4.2 ns


    Original     		PDF 1CY7C1372BV25 CY7C1370BV25 CY7C1372BV25 512Kx36/1Mx18 TMS 3766 DPA 51 7C1370

    CY7C1370B

    Abstract: CY7C1372B 5A- BGA MHZ
    Text: CY7C1370B CY7C1372B PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns


    Original     		PDF CY7C1370B CY7C1372B 512Kx36/1Mx18 CY7C1370B CY7C1372B 5A- BGA MHZ

    CY7C1370B-133AC

    Abstract: 372B CY7C1370B CY7C1370B-200AC CY7C1372B
    Text: 372B CY7C1370B CY7C1372B PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns


    Original     		PDF CY7C1370B CY7C1372B 512Kx36/1Mx18 CY7C1370B-133AC 372B CY7C1370B CY7C1370B-200AC CY7C1372B

    CY7C1370B-133BZC

    Abstract: No abstract text available
    Text: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1370B CY7C1372B 36/1M CY7C1370B/CY7C1372B 36/1M BG119) BB165A) CY7C1370B-133BZC

    CY7C1370BV25

    Abstract: CY7C1372BV25
    Text: CY7C1372BV25 CY7C1370BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200,167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns • Internally synchronized registered outputs eliminate


    Original     		PDF CY7C1372BV25 CY7C1370BV25 36/1M CY7C1370BV25 CY7C1372BV25

    CY7C1370BV25

    Abstract: CY7C1372BV25
    Text: 372BV25 CY7C1370BV25 CY7C1372BV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • No Bus Latency NoBLTM , no dead cycles between write and read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, 4.2 ns


    Original     		PDF 372BV25 CY7C1370BV25 CY7C1372BV25 512Kx36/1Mx18 CY7C1370BV25 CY7C1372BV25

    T1X15

    Abstract: CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X

    vhdl code for dice game

    Abstract: Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet
    Text: Product Selector Guide Communications Products Description Pins Part Number Freq. Range Mbps ICC (mA) Packages* 3.3V SONET/SDH PMD Transceiver 2.5V SiGe Low Power SONET/SDH Transceiver SONET/SDH Transceiver w/ 100K Logic 2.5 G-Link w/ 100K Logic OC-48 Packet Over SONET (POS) Framer


    Original     		PDF OC-48 CYS25G0101DX CYS25G0102 CYS25G01K100 CYP25G01K100 CY7C9536 CY7C955 CY7B952 CY7B951 10BASE vhdl code for dice game Video Proc 3.3V 0.07A 64-Pin PQFP ez811 GRAPHICAL LCD interfaced with psoc 5 cypress ez-usb AN2131QC CYM9239 vhdl code PN 250 code generator CY3649 cy7c63723 Keyboard and Optical mouse program CY7C9689 ethernet

    CY7C1370B

    Abstract: CY7C1370C CY7C1372C
    Text: CY7C1370C CY7C1372C PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns


    Original     		PDF CY7C1370C CY7C1372C 512Kx36/1Mx18 CY7C1370C/CY7C1372C BG119) BB165A) CY7C1370B CY7C1370C CY7C1372C

    CY7C9538

    Abstract: CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c CY7C9538 CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15

    Untitled

    Abstract: No abstract text available
    Text: CY7C1370C CY7C1372C PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns


    Original     		PDF CY7C1370C CY7C1372C 512Kx36/1Mx18 CY7C1370C/CY7C1372C

    DQ214

    Abstract: CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860 MSM7717-01 XCVE-600 pA2240 prbs parity checker and generator RDAT10
    Text: 10, 3610 PRELIMINARY CY7C9536-EVAL POSIC Evaluation Board Introduction Standard MICTOR connectors are used on all buses for external driving and observing signals.This permits the user to directly control all aspects of the board’s operation. Purpose


    Original     		PDF CY7C9536-EVAL CY7C9536-EVAL DQ214 CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860 MSM7717-01 XCVE-600 pA2240 prbs parity checker and generator RDAT10

    nobl sram 1994

    Abstract: CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps nobl sram 1994 CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original     		PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC

    mictor

    Abstract: mictor connector board data Mictor 38 connecter cyp15g0401dx cypress cpld hotlink Mictor connecter CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860
    Text: CYPOSIC2GVC-K PRELIMINARY POSIC2GVC /POSIC2G™ Evaluation Board Purpose This board is intended for two purposes. The first is as a demonstration of the capabilities of the Packet-Over-SONET Integrated Circuit POSIC2GVC device. The second is as a development platform for the system designer who wants to


    Original     		PDF CYS25G0101DX OC-48 Delta39K CY39100V388-200MGC MPC860 CY7C1370B CYS25G0101DX CYP15G0401DX MSM7717-01 mictor mictor connector board data Mictor 38 connecter cyp15g0401dx cypress cpld hotlink Mictor connecter CY39100V388-200MGC CY7C1370B

    T1X15

    Abstract: CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX

    Untitled

    Abstract: No abstract text available
    Text: CY7C1370CV25 CY7C1372CV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns


    Original     		PDF CY7C1370CV25 CY7C1372CV25 512Kx36/1Mx18 CY7C1370CV25/CY7C1372CV25

    Cp5609amt

    Abstract: cp5858am CP5629BM CG5113 PCN030073 W48S111-14G 5L512 CY2292ASI CY2292SL-1V1 CY2292SC-68T
    Text: SEMICONDUCTOR FINAL PRODUCT CHANGE NOTIFICATION PCN: PCN030073 DATE: November 7, 2003 Subject: Prune List Q4, 2003 To: Description of Change: Cypress is officially announcing the obsolescence of these products. Refer to the attached list for the list of products being discontinued.


    Original     		PDF PCN030073 reprrese1/03/03 Cp5609amt cp5858am CP5629BM CG5113 PCN030073 W48S111-14G 5L512 CY2292ASI CY2292SL-1V1 CY2292SC-68T

    CY7C1370C

    Abstract: CY7C1370CV25 CY7C1372C CY7C1372CV25 CY7C1372CV25-200BZC
    Text: CY7C1370CV25 CY7C1372CV25 PRELIMINARY 512Kx36/1Mx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between write and read cycles • Fast clock speed: 250, 225, 200, and 167 MHz • Fast access time: 2.6, 2.8, 3.0, 3.4 ns


    Original     		PDF CY7C1370CV25 CY7C1372CV25 512Kx36/1Mx18 CY7C1370CV25/CY7C1372CV25 BG119) BB165A) CY7C1370C CY7C1370CV25 CY7C1372C CY7C1372CV25 CY7C1372CV25-200BZC

    SDH 209

    Abstract: 1xVC4-16c CY7C9538 CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c SDH 209 1xVC4-16c CY7C9538 CYS25G0101DX VC45V