CY7C1394BV18 Search Results

CY7C1394BV18 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1394BV18		Cypress Semiconductor	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture		Original	PDF
CY7C1394BV18-167BZXC		Cypress Semiconductor	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture		Original	PDF

CY7C1394BV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces	Original	CY7C1393BV18 CY7C1394BV18 CY7C1393BV18, CY7C1394BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces	Original	CY7C1393BV18 CY7C1394BV18 CY7C1393BV18, CY7C1394BV18	PDF
CY7C1393BV18-167BZC Abstract: CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18 Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 PRELIMINARY 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18,512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 250-MHz CY7C1393BV18-167BZC CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz	PDF
CY7C1393BV18-300BZC Abstract: CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18 Text: CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit CY7C1393BV18-300BZC CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18	PDF
CY7C1392BV18 Abstract: CY7C1393BV18 CY7C1394BV18 CY7C1992BV18 Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz Expande78-MHz CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces	Original	CY7C1393BV18 CY7C1394BV18 CY7C1393BV18, CY7C1394BV18	PDF
CY7C1392BV18 Abstract: CY7C1393BV18 CY7C1394BV18 CY7C1992BV18 Text: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 CY7C1992BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 PRELIMINARY 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18,512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1392BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit 300-MHz CY7C1992BV18 BB165E BB165D	PDF
Untitled Abstract: No abstract text available Text: CY7C1393BV18 CY7C1394BV18 18-Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces	Original	CY7C1393BV18 CY7C1394BV18 18-Mbit CY7C1393BV18, CY7C1394BV18	PDF
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC	PDF