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HDD13 Abstract: cy7c2263kv18-450bz 3M Touch Systems Text: CY7C2261KV18, CY7C2276KV18 CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	36-Mbit CY7C2261KV18, CY7C2276KV18 CY7C2263KV18, CY7C2265KV18 CY7C2261KV18 CY7C2276KV18 CY7C2263KV18 HDD13 cy7c2263kv18-450bz 3M Touch Systems
CY7C2263KV18 Abstract: CY7C2261KV18 3M Touch Systems Text: CY7C2261KV18, CY7C2276KV18 CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	36-Mbit CY7C2261KV18, CY7C2276KV18 CY7C2263KV18, CY7C2265KV18 CY7C2261KV18 CY7C2276KV18 CY7C2263KV18 CY7C2263KV18 CY7C2261KV18 3M Touch Systems
cy7c2263kv18-450bz Abstract: 3M Touch Systems Text: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18, CY7C2265KV18 36-Mbit CY7C2263KV18 cy7c2263kv18-450bz 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18, CY7C2265KV18 36-Mbit
Untitled Abstract: No abstract text available Text: CY7C2263KV18/CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18/CY7C2265KV18 36-Mbit CY7C2265KV18
CY7C2263KV18 Abstract: 3M Touch Systems Text: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18, CY7C2265KV18 36-Mbit CY7C2263KV18 CY7C2263KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C2263KV18, CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Configurations Features • Separate independent read and write data ports	Original	PDF	CY7C2263KV18, CY7C2265KV18 36-Mbit
Untitled Abstract: No abstract text available Text: CY7C2263KV18/CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18/CY7C2265KV18 36-Mbit CY7C2265KV18
Untitled Abstract: No abstract text available Text: CY7C2263KV18/CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18/CY7C2265KV18 36-Mbit CY7C2265KV18
Untitled Abstract: No abstract text available Text: CY7C2263KV18/CY7C2265KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • Separate independent read and write data ports	Original	PDF	CY7C2263KV18/CY7C2265KV18 36-Mbit CY7C2265KV18