Untitled
Abstract: No abstract text available
Text: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port
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LU5M31
LU5M31
8b/10b
DS98-351LAN
DS97-447LAN)
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clause 22 phy registers
Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Text: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1
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DS1005
clause 22 phy registers
13007 h3
ali 3602
detail of D 13007 K
mca exam date sheet
1000BASE-X
STS-48
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SMD45
Abstract: SMD34 224 d5 smd zd 15 p240f1 SMD52 SMD46 SMD-42 smd M16 SMD23
Text: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社
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PD98421
PD98421
MHz50
S13650JJ6V0DS
P240F1-80-GA5
SMD45
SMD34
224 d5
smd zd 15
p240f1
SMD52
SMD46
SMD-42
smd M16
SMD23
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Untitled
Abstract: No abstract text available
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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SMD phase shifter 0201
Abstract: ts201S ADSP-TS201SABP-050 ADSP-TS201SABP-060 l3bc
Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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576-ball)
14-channel
32-bit
40-bit
64-bit
BP-576
576-Ball
SMD phase shifter 0201
ts201S
ADSP-TS201SABP-050
ADSP-TS201SABP-060
l3bc
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Supersparc
Abstract: IEEE754 STP1021A
Text: STP1021A July 1997 SuperSPARC -II DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor DESCRIPTION The STP1021A is a new member of the SuperSPARC-II family of microprocessor products. Like its predecessors STP1020N, STP1020 and STP1021 this new part is fully SPARC Version 8 compliant and is completely upward compatible with the earlier SPARC Version 7 implementations running over 9,400 SPARC applications and development
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STP1021A
32-Bit
STP1021A
STP1020N,
STP1020
STP1021)
instructionta32
addr18
data50
Supersparc
IEEE754
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TDSR 5130
Abstract: TDSR 5130 H TDSR 5130 g TDSR SQFP208 SAA6750H SAA7111 SAA7146 iso 13818-2 SAA711x
Text: INTEGRATED CIRCUITS DATA SHEET SAA6750H Encoder for MPEG2 image recording EMPIRE Preliminary specification File under Integrated Circuits, IC02 1998 Sep 07 Philips Semiconductors Preliminary specification Encoder for MPEG2 image recording (EMPIRE) SAA6750H
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SAA6750H
SCA60
545104/750/01/pp64
TDSR 5130
TDSR 5130 H
TDSR 5130 g
TDSR
SQFP208
SAA6750H
SAA7111
SAA7146
iso 13818-2
SAA711x
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clause 22 phy registers
Abstract: No abstract text available
Text: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.2, June 2006 LatticeSC flexiPCS Data Sheet Table of Contents June 2006 Introduction to flexiPCS .1-1
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DS1005
VCC12.
clause 22 phy registers
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EE-68
Abstract: ts201 Embedded Processor Preliminary Data Sheet link port ts201 32X32 ADSP-TS201S l3bc ADSP-TS201SABP-6X ADSP-TS201SABP-X
Text: TigerSHARC Embedded Processor ADSP-TS201S Preliminary Technical Data KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, a Register File, and a Communications Logic
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ADSP-TS201S
576-Ball)
24Mbit
BP-576
ADSP-TS201SABP-X
C00000-0-03/03
BP-576)
EE-68
ts201 Embedded Processor Preliminary Data Sheet
link port ts201
32X32
ADSP-TS201S
l3bc
ADSP-TS201SABP-6X
ADSP-TS201SABP-X
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MI-MV13
Abstract: M4T11 cmos 3.1 megapixel 18 pin image sensor V7514 "Micron Technology" cmos c16
Text: 1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR MT9M413 Micron Part Number: MT9M413C36STC Description The MI-MV13 is a 1,280H x 1,024V 1.3 megapixel CMOS digital image sensor capable of 500 frames-persecond (fps) operation. Its TrueSNAP electronic
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MI-MV13
10-bit
10-bit-wide
09005aef806807ca
MT9M413C36STC
M4T11
cmos 3.1 megapixel 18 pin image sensor
V7514
"Micron Technology" cmos c16
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PB-MV40
Abstract: Photobit MV40 D100 D109 D110 D119 D120 D129 D130
Text: PB-MV40 4 Megapixel CMOS Active-Pixel Digital Image Sensor 2001 Photobit Technology Corporation. All rights reserved. Photobit Technology Corporation is a wholly owned subsidiary of Photobit Corporation. Photobit, the wave and binary symbol, Behind Every Great Digital Image, and TrueBit are registered trademarks-and TrueColor, TrueSNAP Shuttered-Node
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PB-MV40
prod05
D-263
PB-MV40
Photobit
MV40
D100
D109
D110
D119
D120
D129
D130
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GHW Connectors
Abstract: TDQ38 BTA60 bta61 bta80 bta11 BTA100 BTA32 bta50 bta81
Text: Version 1.2 December 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1999 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
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sot23-6 aa3
Abstract: l3bc ST-323-5 ADSP-TS201 SDRAM W17 sot23 micro usb 8pin schematic AE1233-ND p-channel mosfet m21 D44 SOT23-6 B20 SOT23-6
Text: ADSP-TS201S EZ-KIT Lite Evaluation System Manual Revision 1.0, March 2004 Part Number 82-000770-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
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ADSP-TS201S
sot23-6 aa3
l3bc
ST-323-5
ADSP-TS201 SDRAM
W17 sot23
micro usb 8pin schematic
AE1233-ND
p-channel mosfet m21
D44 SOT23-6
B20 SOT23-6
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32x32 Multiplier
Abstract: EE-174 32X32 ADSP-TS201S processor cross reference avr ms1 diagram ADSP-TS201SABP-ENG
Text: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS201S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 24M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package
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ADSP-TS201S
576-Ball)
ADSP-TS201SABP-ENG
24Mbit
BP-576
32x32 Multiplier
EE-174
32X32
ADSP-TS201S
processor cross reference
avr ms1 diagram
ADSP-TS201SABP-ENG
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PB-MV13
Abstract: Photobit PB-1024 PHILIPS mpr24 8097 architecture MV13 DATA-71 data61 Data72 Photobit 720
Text: PB-MV13 20mm CMOS Active-Pixel Digital Image Sensor 2000 Photobit Corporation. All rights reserved. Photobit, the wave and binary symbol, and Behind Every Great Digital Image are registered trademarks, and TrueBit, TrueColor, TrueSNAP Shuttered-Node Active Pixel , Fully Flexible Open Architecture, Serial Host Interface Port, and Leading the Active Pixel Revolution are trademarks, of Photobit Corporation in
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PB-MV13
PB-MV13
280-Pin
Photobit
PB-1024
PHILIPS mpr24
8097 architecture
MV13
DATA-71
data61
Data72
Photobit 720
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clause 22 phy registers
Abstract: No abstract text available
Text: LatticeSC Family flexiPCS Data Sheet DS1005 Version 01.5, March 2007 LatticeSC flexiPCS Data Sheet Table of Contents March 2007 Introduction to flexiPCS .1-1
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10-bit
8b10b
clause 22 phy registers
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74ALVT16652
Abstract: CYNCP80192 CYNSE70032 CYNSE70128
Text: CYNCP80192 CYNCP80192 Network Database Coprocessor Cypress Semiconductor Corporation Rev. * • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 20, 2001 CYNCP80192 CONTENTS 1.0 OVERVIEW . 1
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CYNCP80192
CYNCP80192
74ALVT16652
CYNSE70032
CYNSE70128
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clause 22 phy registers
Abstract: No abstract text available
Text: LatticeSC Family flexiPCS Data Sheet Version 01.0, February 2006 LatticeSC flexiPCS Data Sheet Table of Contents February 2006 Introduction to flexiPCS .1-1
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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Untitled
Abstract: No abstract text available
Text: CS4298 SoundFusion Audio/Modem Codec ’97 AMC’97 FEATURES DESCRIPTION • AC ‘97 2.0 compatible The CS4298 is an AC ‘97 compatible Audio/Mo dem Codec designed for PC multimedia systems. Using the industry leading CrystalClear deltasigma and mixed signal technology, the CS4298 is
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CS4298
CS4298
98-compliant
20-bit
/platform/ac97/
DS315PP2
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Untitled
Abstract: No abstract text available
Text: SONY PRELIMINARY SCM603256A5 Cache Module for PowerPC 603e CPU PowerPC 603e 256KB Secondary Cache Description The SCM603256A5 module belongs to a set of sec ondary caches intended for use with PowerPC 603e based systems. The SCM603256A5 uses two of Sony’s 1M 32Kx32
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SCM603256A5
256KB
603eTM
SCM603256A5
32Kx32
ISB31
SCM603256A4
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supersparc
Abstract: HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33
Text: [ f ^ T l r í A C K j S un M i c r o e l e c t r o n i c s July 1997 SuperSPARC“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the Su p erSPA R C T I fam ily o f m icroprocessor products. L ik e its predeces
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STP1021A
STP1020N,
STP1020
STP1021)
cl277
data12
STP1021APGA-85
STP1021APGA-75
supersparc
HY 1021A
Sun STP1021
3AR3
cap 220 htz
ADA33
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Untitled
Abstract: No abstract text available
Text: STP1091 S un M ic r o e l e c t r o n ic s J u ly 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-perform ance external cache controller for the STP1020 SuperSPARC and STP1021
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STP1091
STP1091
STP1020
STP1021
33x8k
1091PG
STP1020H
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Untitled
Abstract: No abstract text available
Text: IBM25CPC710AB3A100 IBM Dual Bridge and Memory Controller Features • • • • • • • • • • • • • • Up to 100 MHz PowerPC 60x 64-bit bus Supports 100 MHz SDRAM including PC100 I/O for up to 2 MB 8-bit flash ROM 32-bit 33 MHz/64-bit 33-66 MHz async dual bus
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IBM25CPC710AB3A100
64-bit
PC100
32-bit
Hz/64-bit
32x32mm
35jim
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