pll 566
Abstract: pll 565 application pll 565 DJZ capacitor CA1310 565 PLL AD P71 CA10 CA12 elan microelectronics 1999
Text: ICE567 User manual FOR EM78565 EM78566 EM78567 Version 1.0 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: 03 5639977 FAX: (03) 5630118 EM78567/566/565 Manual EM78P567/566/565 Manual
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Original
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ICE567
EM78565
EM78566
EM78567
EM78567/566/565
EM78P567/566/565
EM78R567
DELAY22
1999/Jun/14
pll 566
pll 565 application
pll 565
DJZ capacitor
CA1310
565 PLL
AD P71
CA10
CA12
elan microelectronics 1999
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PDF
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84C300A
Abstract: No abstract text available
Text: Full Duplex 84C 300A 4-Port Fast Ethernet Controller Technology Incorporated PRELIMINARY _April 19, 1996 Features • Low Power CMOS Technology ■ 4-Port Ethernet Controller Optimized for Note: Check for latest Data Sheet revision
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84C300A
100Base-T4
100Base-TX,
100Base-FX
10Base-T
ANSI/IEEE802
10Base-5)
10Base-2)
10Base-T)
10MBlt/sec
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PDF
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Untitled
Abstract: No abstract text available
Text: « LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FE A T U R E S PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one
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SY100S390
SY100S390
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84C30A
Abstract: 051b3
Text: Full Duplex S4C30A 4-Port Technology Incorporated Ethernet Controller PRELIMINARY April 19, 1996 Features • ■ Note: Check for latest Data Sheet revision before starting any designs. Low Power CMOS Technology ■ Meets A NSI/IEEE802.3 and ISO 8802-3 Standards
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84C30A
ANSI/IEEE802
10Base-5)
10Base-T)
MD400151/A
84C30A
051b3
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PDF
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SY-510
Abstract: 7006L 7006S
Text: OlDT HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Features * * * * IDT7006S/L one d evice_ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling
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IDT7006S/L
20/25/35/55/70ns
75/77/20/25/35l55ns
IDT7006S
750mW
IDT7006L
700mW
IDT7006
SY-510
7006L
7006S
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palc22v10d programming guide
Abstract: No abstract text available
Text: Flash Erasable, Reprogrammable CMOS PAL Device Features • Advanced second-generation PAL architecture • Low power — 90 mA max. commercial 10 ns — 130 mA max. commercial (7.5 ns) • CMOS Flash EPROM technology for electrical erasabllity and reprogrammablllty
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133-MHz
110-MHz
15-ns
25-ns
PALC22V10D-15JC
PALC22V10D-15PC
PALC22V1OD-15JI
PALC22V10D-15PI
PALC22V1
OD-15DMB
palc22v10d programming guide
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s3102
Abstract: MS310256-15PC
Text: MOSEL MS310256 32,768x8 CMOS Mask Programmable ROM FEATURES DESCRIPTION • Access time: 150ns max The MS310256 is a high performance Read Only Memory organized as 32,768 words by 8 bits. It is designed to be compatible with all microprocessors and similar applications where high performance
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150ns
MS310256
768x8
MS310256
PID031
MS310256-15PC
MS310256-15XC
P28-3
s3102
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Untitled
Abstract: No abstract text available
Text: 11S8>s\i jdt HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM IDT7007S/L Integrated Device Technology, Inc. FEATURES: • True Dual-Ported memory cells which allow simulta neous reads of the same memory location • High-speed access — Military: 25/35/55ns max.)
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IDT7007S/L
25/35/55ns
20/25/35/55ns
IDT7007S
750mW
IDT7007L
IDT7007
MIL-STD-883,
80-pin
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Untitled
Abstract: No abstract text available
Text: HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS IDT71V321S/L IDT71V421S/L Features * * High-speed access ♦ BUSY output flag on IDT71V321; BUSY input on IDT71V421 - Industrial: 25ns max. * Fully asynchronous operation from either port - Commercial: 25135155ns (max.)
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IDT71V321S/L
IDT71V421S/L
IDT71V321;
IDT71V421
25135155ns
IDT71V321/IDT7W421S
325mW
52-pin
64-pin
IDT7IV321/V421L
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SY 3803 12A
Abstract: dw02a
Text: i t IDT H IG H - S P E E D C T A T ir ^ d a u ^ L * P O R T S T A T IC R A M Featu res: * True Dual-Ported memory cells which allow simultaneous access of the same memory location * High-speed access - * industrial: 35ns max. Commercial: 15/2Q/25/35/55ns (max.)
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15/2Q/25/35/55ns
IDT70V27S
500mW
IDT70V27L
660mW
IDT70V27
SY 3803 12A
dw02a
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PDF
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Untitled
Abstract: No abstract text available
Text: Full Duplex Technology, Incorporated Full Duplex CMOS Ethernet 10/100 Mega Bit/Sec Data Link Controller Preliminary _ April 19, 1996 Features • Low Power CMOS Technology ■ 10/100 MBit Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router,
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ANSI/IEEE802
10Base-5)
10Base-2)
10Base-T)
100Base-T4,
100Base-TX
10MBlt/sec
80C300
MD400145/C
80C300
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PDF
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Untitled
Abstract: No abstract text available
Text: * L O W -R O W ER 9-BP SY N E R G Y S Y 100SJ21 IN VER TER S E M IC O N D U C T O R F EA TU R E S D E S C R IP TIO N • Max. propagation delay of 700ps The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single
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100SJ21
700ps
F100K
24-pin
28-pin
SY100S321
SY100S321FC
SY100S321JC
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