Untitled
Abstract: No abstract text available
Text: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26101
DS26101
56-G6017-001C
X256-1*
DS26101N
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motorola bts maintenance
Abstract: g6017
Text: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26101
56-G6017-001C
X256-1*
DS26101N
motorola bts maintenance
g6017
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SAD 512
Abstract: CS61584A SAD assembly cirrus Logic Marking Code
Text: 11/16/00 Errata: CS61584A Revision E Reference CS61584A Data Sheet revision DS261PP4 dated JAN ‘99 This document lists the errata for Revision E of the CS61584A device, and describes the differences between Revision E and the referenced Data Sheet. 1. Quartz Crystal Loading Issue
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CS61584A
DS261PP4
ER261C4
ER213I1
SAD 512
SAD assembly
cirrus Logic Marking Code
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11-B
Abstract: 11-D DS26101
Text: DS26101 8-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26101
DS26101
11-B
11-D
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RLCD14
Abstract: RLCD10
Text: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26102
16-Port
DS26101
56-G6017-001C
X256-1*
DS26101N
RLCD14
RLCD10
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crystal oscillator marking
Abstract: CS61584A
Text: 02/10/99 Errata: CS61584A Revision D Reference CS61584A Data Sheet revision DS261PP4 dated JAN ‘99 This document is an errata for Revision D of the CS61584A device, and describes the differences between Revision D and the referenced data sheet. Revision E is expected to
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CS61584A
DS261PP4
-14dB
-11dB
-12dB
-20dB
crystal oscillator marking
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11-B
Abstract: 11-D DS26101 bts 122 E1 frame
Text: DS26101 8-Port TDM-to-ATM PHY www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26101 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26101
DS26101
11-B
11-D
bts 122
E1 frame
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11-D
Abstract: DS26102 11-B RLCD10 E1 frame
Text: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26102
16-Port
DS26102
11-D
11-B
RLCD10
E1 frame
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DS21352
Abstract: DS21354 DS21455 DS21458 DS2155 DS21552 DS21554 DS2156 DS26101 DS26102
Text: Maxim/Dallas > App Notes > TELECOM Keywords: Loopback, loopback operation, DS2156, DS26101, DS26102, Utopia, LLB, RLB, FLB, PLB, DLB, local loopback, remote loopback, framer loopback, payload loopback, diagnostic loopback, per-channel loopback Sep 10, 2004
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DS2156,
DS26101,
DS26102,
DS2155:
DS21552:
DS21554:
DS2156:
DS21Q352:
DS21Q354:
DS21Q55:
DS21352
DS21354
DS21455
DS21458
DS2155
DS21552
DS21554
DS2156
DS26101
DS26102
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DS-261
Abstract: dma controller VERILOG DS261 PCI-X verilog code for pci halfbridge design 4 channels design of dma controller using verilog
Text: DS261 v1.0 June 23, 2003 PCI-X/PCI HalfBridge Reference Design for Virtex-II Pro, Virtex-II, and Virtex-E FPGAs Product Overview Features • Asynchronous clocks for PCI-X and FPGA operation • • Up to eight DMA Controller(s) Free with purchase of Xilinx PCI-X 64/66 Core
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DS261
66MHz/64-bit
Hz/64-bit
DS-261
dma controller VERILOG
DS261
PCI-X
verilog code for pci
halfbridge design
4 channels design of dma controller using verilog
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Untitled
Abstract: No abstract text available
Text: DS26102 16-Port Transmission Convergence Device www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26102
16-Port
DS26101
56-G6017-001C
X256-1*
DS26101N
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RLCD15
Abstract: 11-B 11-D DS26102 of bc 237 b E1 frame
Text: DS26102 16-Port TDM-to-ATM PHY www.maxim-ic.com GENERAL DESCRIPTION FEATURES On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering up to 4 cells , HEC generation and insertion, cell scrambling, and converts the data
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DS26102
16-Port
DS26102
RLCD15
11-B
11-D
of bc 237 b
E1 frame
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DS377
Abstract: No abstract text available
Text: IDT 89EB-LOGAN-19 Evaluation Board Manual Evaluation Board: 18-692-001 February 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. 2011 Integrated Device Technology, Inc.
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89EB-LOGAN-19
R1431
R1428
R1425
EB-LOGAN-19
SCH-PESEB-002
DS377
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TSSOP-16
Abstract: No abstract text available
Text: Preliminary EUP2618 Triple Adjustable Output TFT-LCD DC-DC Converters DESCRIPTION FEATURES The EUP2618 triple-output DC-DC converter provides the regulated voltages required by active-matrix, thin-film transistor TFT liquid-crystal displays (LCDs). One high-power DC-DC converter and two low-power charge
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EUP2618
EUP2618
DS2618
TSSOP-16
TSSOP-16
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CS61584A
Abstract: No abstract text available
Text: CS61584A Product Technical Brief Reading and Writing Waveforms on the CS61584A The Arbitrary Waveform Generator AWG is a unique feature of Crystal LIU’s that allows the customization of the output waveform for non-standard terminations. The function of the AWG on the
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CS61584A
CS61584A
DS261PP4)
AN07REV2)
TB261BPP1
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CON12
Abstract: CS61584A CS61584A-IL3 CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY
Text: CS61584A Dual T1/E1 Line Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications
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CS61584A
TR-NET-00499
CS61584A
DS261PP5
CON12
CS61584A-IL3
CS61584A-IL5
CS61584A-IQ3
CS61584A-IQ5
BIPOLAR MEMORY
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ASD 800 ASD 810
Abstract: LS 1017 TRANSFORMER BTS 8800 CON12 CS61584A CS61584A-IL5 CS61584A-IQ3 CS61584A-IQ5 BIPOLAR MEMORY RV-1 1k
Text: CS61584A CS61584A Dual Dual T1/E1 T1/E1 Line Line Interface Interface Features – AT&T Publication 62411 – ETSI ETS 300 011, 300 233, CTR 12, TBR 13 l Dual T1/E1 Line Interface Volt and 5 Volt Versions l Crystal-less Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011
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CS61584A
TR-NET-00499
CS61584A
DS261F1
ASD 800 ASD 810
LS 1017 TRANSFORMER
BTS 8800
CON12
CS61584A-IL5
CS61584A-IQ3
CS61584A-IQ5
BIPOLAR MEMORY
RV-1 1k
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max14574
Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Text: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.
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Untitled
Abstract: No abstract text available
Text: Data Sheet AKU340 Analog MEMS Microphone Data Sheet AKU340 Analog MEMS Microphone Datasheet Part number s AKU340 Package type LGA, bottom port, metal lid Data sheet revision 1.0 Release date 4 June 2013 Document number DS26-1.0 AKU340 Data Sheet Notes Specifications are subject to change without notice.
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AKU340
DS26-1
AKU340
04Jun2013
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AMI 52 732 V
Abstract: ACT 4060 ASH
Text: CS61584A Product Databook FEATURES n Dual T1/E1 Line Interface n 3.3 Volt and 5 Volt Versions Dual T1/E1 Line Interface n Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications DESCRIPTION n Matched Impedance Transmit Drivers
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CS61584A
TR-NET-00499
AMI 52 732 V
ACT 4060 ASH
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IR DATABOOK SCR
Abstract: cmos logic databook BTS 8800 COMCLOK 13.56 CON12 line output transformer for television Transformer te-e TTL databook TTL databook application CS61584A
Text: CS61584A Product Databook =CIRRUS LOGIC FEATURES • Dual T1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions D ual T1/E1 Line In terface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications ■ Matched Impedance Transmit Drivers
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ST5175T
TD38-1505A
PE-65388
PE-65770
PE-65838
PE-68674
PE-65870
T1016
T1072
ST5112
IR DATABOOK SCR
cmos logic databook
BTS 8800
COMCLOK 13.56
CON12
line output transformer for television
Transformer te-e
TTL databook
TTL databook application
CS61584A
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TD38-1505A
Abstract: rneg2
Text: P R E L IM IN A R Y 8/ 11/97 A Cirrus Logic Company C S 6 1 5 8 4 A Dual T1/E1 Line Interface Features General Description • Dual T1/E1 Line Interface The CS61584A is a dual line interface for T1/E1 appli cations, designed for high-voiume cards where low
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CS61584A
DS261PP2
TD38-1505A
rneg2
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cn/A/U 237 BG
Abstract: No abstract text available
Text: CS61584A = Product Databook CIRRUS LOGIC FEATURES • DualT1/E1 Line Interface ■ 3.3 Volt and 5 Volt Versions Dual T1/E1 Line Interface ■ Crystalless Jitter Attenuator Meets European CTR 12 and ETSI ETS 300 011 Specifications DESCRIPTION ■ Matched Impedance Transmit Drivers
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CS61584A
DS261PP4
cn/A/U 237 BG
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Untitled
Abstract: No abstract text available
Text: Semiconduc DS26S10 ^ j^ N a tio n a l or DS26S10 Quad Bus Transceiver General Description The D S 26S 10 is a quad Bus Transceiver consisting of 4 high speed bus drivers with open-collector outputs capable of sinking 100 mA at 0.8V and 4 high speed bus receivers.
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DS26S10
DS26S10
S26S10
S26S10
DS2610
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