DSEI 12 X 61 10 B Search Results

DSEI 12 X 61 10 B Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
7N60B equivalent Abstract: 18N50 equivalent ixgh 1499 MOSFET smd 4407 IXDD 614 C 547 B W57 BJT transistor r1275ns20l R1271ns12C IXYS CS 20-22 MOF1 IXTP 220N04T2 Text: Contents Page General Contents QA and Environmental Management Systems Alphanumeric Index Symbols and Terms Nomenclature Patents and Intellectual Property I II III XVIII XX XXII CLARE Optically Isolated Solid State Relays Optically Isolated AC-Power Switches	Original	PDF	MS-013 10-Pin 5M-1994 MO-229 7N60B equivalent 18N50 equivalent ixgh 1499 MOSFET smd 4407 IXDD 614 C 547 B W57 BJT transistor r1275ns20l R1271ns12C IXYS CS 20-22 MOF1 IXTP 220N04T2
D950 Abstract: D952 ST18952 Ya13 SCR SN 102 YBs 70 YA11 Text: ST18952 DIGITAL SIGNAL PROCESSOR DSP CHIP PRELIMINARY DATA • ■ ■ Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit ■ Fast and flexible buses ■ 66MIPS - 15 ns instruction cycle time 16.5 Kwords data memory (RAM)	Original	PDF	ST18952 66MIPS D950 D952 ST18952 Ya13 SCR SN 102 YBs 70 YA11
PIR CONTROLLER LP 0001 Abstract: ED-9P PDCR 912 pdcr 921 23D31 D950 D950CORE ST18-AU1 dialnorm dynamic range dsei 17-12 Text: ST18-AU1 SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER PRELIMINARY DATA FEATURES • ■ ■ ■ Single chip multi-function audio decoder able to decompress DOLBY AC-3, MPEG-1 and MPEG-2 audio streams. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Emulation unit and TAP	Original	PDF	ST18-AU1 PIR CONTROLLER LP 0001 ED-9P PDCR 912 pdcr 921 23D31 D950 D950CORE ST18-AU1 dialnorm dynamic range dsei 17-12
vhdl code for 8-bit serial adder Abstract: dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder Text: D950-CORE 16-Bit Fixed Point Digital Signal Processor DSP Core • ■ ■ ■ ■ OUTPUT CLOCKS 16 XA-bus 16 YA-bus 16 CALCULATION 16 UNIT PROGRAM CONTROL UNIT 3 ID-bus 16 IA-bus 16 DATA MEMORY 6 ADDRESS PROGRAM MEMORY ■ UNIT VDD VSS ■ DATA CALCULATION	Original	PDF	D950-CORE 16-Bit 16-ights vhdl code for 8-bit serial adder dse1 D950-CORE ieee floating point alu in vhdl vhdl code for 16 bit barrel shift register vhdl code for 8-bit adder
eel 19 2005 transformer Abstract: eel 19 2005 transformer spellman igbt gate driver circuit schematic schematic diagram igbt inverter welding machine Text: HIGH VOLTAGE REFERENCE MANUAL 4/2014 REV. 4 Copyright 2014 Spellman High Voltage Electronics Corp. T E C H N I C A L R E S O U R C E S M A N U A L TABLE OF CONTENTS Spellman USA and Corporate HQ 475 Wireless Blvd. Hauppauge, NY 11788 United States tel: +1-631-630-3000	Original	PDF	B-720, eel 19 2005 transformer eel 19 2005 transformer spellman igbt gate driver circuit schematic schematic diagram igbt inverter welding machine
Untitled Abstract: No abstract text available Text: LINEAR INTEGRATED CIRCUIT KA2810 VCM + SPM DRIVER for 3.5 Inch HDD The KA2810 is one chip IC designed to drive Spindle Motor SPM and Voice Coil Motor(VCM) in 3.5 inch Hard Disk Driver (HDD). The Analog Servo Control function can be performed well by built-in High-speed OPAmp and Comparators.	OCR Scan	PDF	KA2810 KA2810 DAN212K MBR130T3 RB4110
Untitled Abstract: No abstract text available Text: n = T S G S -IH O M S O N ">Ji» [MI»i[LiÊiniB R!lDÊê ST 18952 DIGITAL SIGNAL P R O C ESSO R DSP) CHIP P R ELIM IN A R Y DATA • Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit ■ Fast and flexible buses	OCR Scan	PDF	66MIPS ST18952 ST18952 m52BC041, ST18952X66S
Untitled Abstract: No abstract text available Text: r=Z SGS-THOMSON ST18952 DIGITAL SIGNAL P R O C E SSO R DSP CHIP PR E LIM IN A R Y DATA • Programmable D950 Core ■ Data calculation unit ■ Address calculation unit ■ Program control unit 16.5 Kwords data memory TAP ■ Fast and flexible buses ■ 66MIPS - 1 5 ns instruction cycle time	OCR Scan	PDF	ST18952 66MIPS ST18952X66S D950Core
Untitled Abstract: No abstract text available Text: SGS-THOMSON ilUHgüMMÊi D950-CQRE 16-Bit Fixed Point Digital Signal Processor DSP Core PRELIMINARY DATA P erform ance • 66 Mips - 15ns instruction cycle time M em ory O rgan izatio n ■ HARVARD architecture ■ Two 64k x 16-bit data memory spaces ■ One 64k x 16-bit program memory space	OCR Scan	PDF	D950-CQRE 16-Bit 40-bit
Untitled Abstract: No abstract text available Text: DALLAS SEMICONDUCTOR DS3134 Preliminary Data Sheet V5 September 1, 1999 DALLAS SEMICONDUCTOR DS3134 CHATEAU CHAnnelized T1 and E1 And Universal HDLC CONTROLLER 256 Channel HDLC Controller that Supports up to 56 T1 or E1 Lines or Two T3 Lines Preliminary Data Sheet	OCR Scan	PDF	DS3134 DS3134 DS21FF42 DS21FT42