Untitled
Abstract: No abstract text available
Text: DATA SHEET 256M bits SDRAM EDS2532AABH-75 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.
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Original
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EDS2532AABH-75
EDS2532AA
90-ball
133MHz
M01E0107
E0493E20
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PDF
|
Untitled
Abstract: No abstract text available
Text: DATA SHEET 256M bits SDRAM EDS2532AABH-75 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.
|
Original
|
EDS2532AABH-75
EDS2532AA
90-ball
133MHz
M01E0107
E0493E20
|
PDF
|
EDS2532AABH-75
Abstract: No abstract text available
Text: DATA SHEET 256M bits SDRAM EDS2532AABH-75 8M words x 32 bits Description Pin Configurations The EDS2532AA is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.
|
Original
|
EDS2532AABH-75
EDS2532AA
90-ball
133MHz
M01E0107
E0493E20
EDS2532AABH-75
|
PDF
|