DDR200
Abstract: DDR266 DDR333 pasr
Text: Last Updated: Sep. 2004 Mobile DDR/SDR PART NUMBERING HY XX X X X X X X X X - X X HYNIX MEMORY TEMPERATURE 5 5M : Commercial 0℃~70℃ BLANK F E I PRODUCT FAMILY : Mobile SDR : Mobile DDR : PDA (-25℃~70℃) : Extended (-25℃~85℃) : Industrial(-40℃~85℃)
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166MHz,
133MHz,
105MHz,
66MHz,
DDR333
DDR266
DDR200
DDR266
DDR333
pasr
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PDF
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HY5MS5B6BLFP
Abstract: HY5MS5B6BL
Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M 8Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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128Mbit
8Mx16bit)
128Mbit
16bit)
H5MS1262EFP
16bits)
HY5MS5B6BLFP
HY5MS5B6BL
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PDF
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Untitled
Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Specification of 512Mb 16Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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512Mbit
512Mb
16Mx32bit)
512Mbit
32bit)
H5MS5122DFR
H5MS5132DFR
32bits)
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PDF
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h5ms1g22
Abstract: No abstract text available
Text: 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb 32Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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32Mx32bit)
32bit)
H5MS1G22MFP
H5MS1G32MFP
h5ms1g22
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PDF
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hynix mcp
Abstract: HY5MS5B6BL H5MS1262EFP 2Mx16
Text: 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M 8Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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128Mbit
8Mx16bit)
128Mbit
16bits)
16bit)
H5MS1262EFP
00Typ.
hynix mcp
HY5MS5B6BL
2Mx16
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PDF
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hynix mcp
Abstract: DDR370 H5MS2532JFR H5MS2
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Specification of 256Mb 8Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256Mbit
256Mb
8Mx32bit)
256MBit
32bits)
32bit)
H5MS2622JFR
H5MS2532JFR
hynix mcp
DDR370
H5MS2
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PDF
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H5MS5122DFR
Abstract: H5MS5122DFR-J3M DDR333 DDR400 h5ms H5MS5132DFR
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Specification of 512Mb 16Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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512Mbit
512Mb
16Mx32bit)
512Mbit
32bit)
H5MS5122DFR
H5MS5132DFR
32bits)
H5MS5122DFR-J3M
DDR333
DDR400
h5ms
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PDF
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H5MS2562JFR
Abstract: H5MS2 h5ms2562jfr-j3m H5MS2562
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb 16Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256Mbit
256Mb
16Mx16bit)
256Mbit
16bits)
16bit)
H5MS2562JFR
00Typ.
H5MS2
h5ms2562jfr-j3m
H5MS2562
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PDF
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H5MS2562
Abstract: H5MS2562JFR hynix mcp H5MS2562JFR-J3M DDR370 16M X 32 SDR SDRAM H5MS256
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb 16Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256Mbit
256Mb
16Mx16bit)
256Mbit
16bits)
16bit)
H5MS2562JFR
00Typ.
H5MS2562
hynix mcp
H5MS2562JFR-J3M
DDR370
16M X 32 SDR SDRAM
H5MS256
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PDF
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hynix memory lpddr
Abstract: DDR200 DDR266 DDR333 RA12 16Mx16bit HY5MS5B6ALFP
Text: 256MBit MOBILE DDR SDRAMs based on 4M x 4Bank x16 I/O Document Title 256MBit 4Bank x 4M x 16bits MOBILE DDR SDRAM Memory Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Feb.2006 Preliminary Note 1) Now under evaluation by the Hynix Development Division.
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256MBit
256MBit
16bits)
11Preliminary
16Mx16bit)
00Typ.
hynix memory lpddr
DDR200
DDR266
DDR333
RA12
16Mx16bit
HY5MS5B6ALFP
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PDF
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H5MS1G62
Abstract: H5MS1G62MFP-J3M H5MS1G62MFP hynix mcp h5ms1g DDR400 ap die hen mcp H5MS1G62MFP-K3M
Text: 1Gbit MOBILE DDR SDRAM based on 16M x 4Bank x16 I/O Specification of 1Gb 64Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 16,777,216 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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64Mx16bit)
16bit)
H5MS1G62MFP
page22)
00Typ.
H5MS1G62
H5MS1G62MFP-J3M
hynix mcp
h5ms1g
DDR400
ap die hen mcp
H5MS1G62MFP-K3M
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PDF
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H5MS5162
Abstract: H5MS5162DFR h5ms5162dfr-j3m hynix mcp DDR333 DDR370 DDR400
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb 32Mx16bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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512Mbit
512Mb
32Mx16bit)
512Mbit
16bit)
H5MS5162DFR
16bits)
H5MS5162
h5ms5162dfr-j3m
hynix mcp
DDR333
DDR370
DDR400
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PDF
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H5MS1G22
Abstract: h5ms1g H5MS1G22MFP H5MS1G32MFP hynix mcp
Text: 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb 32Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 8,388,608 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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32Mx32bit)
32bit)
H5MS1G22MFP
H5MS1G32MFP
page23)
100mA
120mA
450uA
500uA
H5MS1G22
h5ms1g
hynix mcp
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PDF
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Untitled
Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Specification of 256Mb 8Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256Mbit
256Mb
8Mx32bit)
256MBit
32bits)
32bit)
H5MS2622JFR
H5MS2532JFR
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PDF
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hynix ddr ram
Abstract: H5MS1222EFP
Text: 128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O Specification of 128M 4Mx32bit Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 1,048,576 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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128Mbit
4Mx32bit)
128Mbit
32bit)
H5MS1222EFP
32bits)
hynix ddr ram
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PDF
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Untitled
Abstract: No abstract text available
Text: 256MBit MOBILE DDR SDRAMs based on 4M x 4Bank x16 I/O Document Title 256MBit 4Bank x 4M x 16bits MOBILE DDR SDRAM Memory Revision History Revision No. History Draft Date Remark 1.0 Release Aug. 2006 Final This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256MBit
256MBit
16bits)
16Mx16bit)
00Typ.
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PDF
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HY5MS5B2LFP
Abstract: No abstract text available
Text: 256MBit MOBILE DDR SDRAMs based on 2M x 4Bank x32 I/O Document Title 256MBit 4Bank x 2M x 32bits MOBILE DDR SDRAM Memory Revision History Revision No. History Draft Date Remark 1.0 Release Aug. 2006 Final This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256MBit
256MBit
32bits)
8Mx32bit)
HY5MS5B2LFP
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PDF
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HY5MS5B6BL
Abstract: HY5MS5B6BLFP
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit 4Bank x 4M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Apr. 2007 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
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Original
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256Mbit
256Mbit
16bits)
16bit)
00Typ.
HY5MS5B6BL
HY5MS5B6BLFP
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PDF
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Untitled
Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit 4Bank x 2M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Apr. 2007 Preliminary 0.2 - Updated IDD4R values May. 2007 Preliminary
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Original
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256Mbit
256MBit
32bits)
LPDDR266/200
32bit)
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PDF
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HY5MS5B2ALFP
Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit 4Bank x 2M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Apr. 2007 Preliminary 0.2 Updated IDD4R values May. 2007 Preliminary
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Original
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256Mbit
256MBit
32bits)
32bit)
HY5MS5B2ALFP
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PDF
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Untitled
Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit 4Bank x 2M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 Initial Version for Reduced Page Size Option Mar. 2008 1.0 Final Version
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Original
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256Mbit
256MBit
32bits)
32bit)
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PDF
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Untitled
Abstract: No abstract text available
Text: 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit 4Bank x 4M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 - Initial Draft Apr. 2007 1.0 - Added some notes for operating voltage and temperature
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Original
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256Mbit
256Mbit
16bits)
LPDDR266/200
16bit)
00Typ.
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PDF
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LPDDR200
Abstract: HY5MS7B6BLFP
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit 4Bank x 8M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram
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Original
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512Mbit
512Mbit
16bits)
LPDDR266
16bit)
00Typ.
LPDDR200
HY5MS7B6BLFP
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PDF
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Untitled
Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit 4Bank x 4M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram
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Original
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512Mbit
512MBit
32bits)
LPDDR333
32bit)
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PDF
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