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    IEEE 802.3 CLAUSE 31 Search Results

    IEEE 802.3 CLAUSE 31 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LBAA0QB1SJ-295 Murata Manufacturing Co Ltd SX1262 MODULE WITH OPEN MCU Visit Murata Manufacturing Co Ltd
    GRM-KIT-OVER100-DE-D Murata Manufacturing Co Ltd 0805-1210 over100uF Cap Kit Visit Murata Manufacturing Co Ltd
    LBUA5QJ2AB-828 Murata Manufacturing Co Ltd QORVO UWB MODULE Visit Murata Manufacturing Co Ltd
    LXMSJZNCMH-225 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd
    LXMS21NCMH-230 Murata Manufacturing Co Ltd Ultra small RAIN RFID chip tag Visit Murata Manufacturing Co Ltd

    IEEE 802.3 CLAUSE 31 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    mtd981a

    Abstract: 100BASE-FX NC12 NC13 "clock collision" nrzi circuit diagram MLT-3 NC19 "network interface cards"
    Text: MTD981A MYSON TECHNOLOGY 10/100 Ethernet Transceiver FEATURES • · · · · · · · · 10BASE-T, 100BASE-TX, and 100BASE-FX IEEE-802.3 compliant transmit and receive functions IEEE 802.3u Clause 28 compliant Auto-Negotiation function Full duplex operation capable


    Original     		MTD981A 10BASE-T, 100BASE-TX, 100BASE-FX IEEE-802 100-pin MTD981A MTD981AG My3045 NC12 NC13 "clock collision" nrzi circuit diagram MLT-3 NC19 "network interface cards" PDF

    SFF-8665

    Abstract: TIA-604-5
    Text: WWW.PSM4.ORG 100G PSM4 Specification Parallel Single Mode 4 lane 9/15/2014 Version 2.0 September 15, 2014 100G PSM4 Specification This technical document has been created by the PSM4 MSA group. However it is not a warranted document, each transceiver supplier will have their own datasheet. If the user wishes to find a


    Original     		PDF

    sgmii xilinx

    Abstract: traffic light controller vhdl coding sgmii sfp virtex IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 ENG-46158 1000BASE-X IEEE 802.3 Clause 39 VHDL code for traffic light controller sgmii mode sfp
    Text: Ethernet 1000BASE-X PCS/PMA or SGMII v10.2 DS264 June 24, 2009 Product Specification Introduction LogiCORE IP Facts Core Specifics The LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller MAC or


    Original     		1000BASE-X DS264 1000BASE-X ENG-46158) sgmii xilinx traffic light controller vhdl coding sgmii sfp virtex IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 ENG-46158 IEEE 802.3 Clause 39 VHDL code for traffic light controller sgmii mode sfp PDF

    ENG-46158

    Abstract: verilog hdl code for traffic light control traffic light controller vhdl coding IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 verilog coding using instantiations 1000BASE-X sgmii xilinx 1000BASE-LX GTX 460
    Text: Ethernet 1000BASE-X PCS/PMA or SGMII v10.3 DS264 September 16, 2009 Product Specification Introduction LogiCORE IP Facts Core Specifics The LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller MAC or


    Original     		1000BASE-X DS264 1000BASE-X ENG-46158 verilog hdl code for traffic light control traffic light controller vhdl coding IEEE 802.3 Clause 38 vhdl code for ethernet mac spartan 3 verilog coding using instantiations sgmii xilinx 1000BASE-LX GTX 460 PDF

    Internal diagram of ic 7495

    Abstract: LU3X54FTL IC 7495 pin configuration
    Text: Product Brief May 1998 LU3X54FTL QUAD-FET for 10Base-T/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3U 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL


    Original     		LU3X54FTL 10Base-T/100Base-TX/FX 100Base-FX LU3X54FTL 10Base-T PN98-155LAN Internal diagram of ic 7495 IC 7495 pin configuration PDF

    Internal diagram of ic 7495

    Abstract: LU3X54FT "Fast Link Pulse"
    Text: Product Brief May 1998 LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Features 100 Mbits/s FX Transceiver 10 Mbits/s Transceiver • Compatible with IEEE 802.3U 100Base-FX standard ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL PECL


    Original     		LU3X54FT 10Base-T/100Base-TX/FX 100Base-FX LU3X54FT 10Base-T PN98-140LAN Internal diagram of ic 7495 "Fast Link Pulse" PDF

    AFBR-703ASDZ

    Abstract: IEC-61000-4-2 RIN12OMA SDD11 SFF-8431 10G SFP SCD11 042UI PRBS31
    Text: AFBR-703ASDZ 850nm Digital Diagnostic SFP+ Transceiver for 10Gb Ethernet 10GBASE-SR Characterization Report Description The AFBR-703ASDZ optical transceivers are reduced cost SFP+ 10 Gigabit Ethernet 10GBASE-SR modules for use on multimode fiber. • Receiver Rise and Fall Times RX TR and RX TF


    Original     		AFBR-703ASDZ 850nm 10GBASE-SR AFBR-703ASDZ 10GBASE-SR SFF-8431 SDD22 SCC22) AV02-1900EN IEC-61000-4-2 RIN12OMA SDD11 10G SFP SCD11 042UI PRBS31 PDF

    AFBR-703SDZ

    Abstract: IEC-61000-4-2 RIN12OMA SDD11 SFF-8431 10G SFP PRBS31
    Text: AFBR-703SDZ 850nm Digital Diagnostic SFP+ Transceiver for 10Gb Ethernet 10GBASE-SR Characterization Report Description The AFBR-703SDZ optical transceivers are reduced cost SFP+ 10 Gigabit Ethernet 10GBASE-SR modules for use on multimode fiber. • Receiver Rise and Fall Times RX TR and RX TF


    Original     		AFBR-703SDZ 850nm 10GBASE-SR AFBR-703SDZ 10GBASE-SR SFF-8431 SDD22 SCC22) AV02-1899EN IEC-61000-4-2 RIN12OMA SDD11 10G SFP PRBS31 PDF

    the RMII Consortium Specification

    Abstract: LC10 LC100 LS10 LS100 LU3X36FTR PN99-054LAN RMII Consortium
    Text: Product Brief March 1999 LU3X36FTR HEX-FET Fast Ethernet Transceiver for 10Base-T/100Base-TX/FX Overview The LU3X36FTR is a six-channel, single-chip complete transceiver designed specifically for dual-speed 10Base-T, 100Base-TX, and 100Base-FX switches and repeaters. It supports simultaneous operation in


    Original     		LU3X36FTR 10Base-T/100Base-TX/FX LU3X36FTR 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. the RMII Consortium Specification LC10 LC100 LS10 LS100 PN99-054LAN RMII Consortium PDF

    130nm CMOS

    Abstract: P802 TLK3118 MDIO clause 45 MDIO clause 45 specification
    Text: TLK3118 REDUNDANT XAUI TRANSCEIVER SLLS609 − JANUARY 2004 D D D D D D D D D TLK3118 TDP/N[3:0]0 TCLK RDP/N[3:0]0 4 4 TD 31.0 TC(3.0) RCLK RD(31.0) TDP/N[3:0]1 RC(3.0) RDP/N[3:0]1 4 4 description The TLK3118 is a flexible, redundant XAUI serial transceiver that is compliant to 10-Gbps Ethernet XAUI


    Original     		TLK3118 SLLS609 TLK3118 10-Gbps 130nm CMOS P802 MDIO clause 45 MDIO clause 45 specification PDF

    the RMII Consortium Specification

    Abstract: MDIO clause 45 specification MDIO clause 22 RMII Consortium SMII specification LC10 LC100 LS10 LS100 LU3X312FTR
    Text: Product Brief June 1999 LU3X312FTR 12-Port Transceiver for 10Base-T/100Base-TX/FX Overview The LU3X312FTR is an twelve-channel, single-chip complete transceiver designed specifically for dualspeed 10Base-T, 100Base-TX, and 100Base-FX switches and repeaters. It supports simultaneous


    Original     		LU3X312FTR 12-Port 10Base-T/100Base-TX/FX LU3X312FTR 10Base-T, 100Base-TX, 100Base-FX 100Base-FX. the RMII Consortium Specification MDIO clause 45 specification MDIO clause 22 RMII Consortium SMII specification LC10 LC100 LS10 LS100 PDF

    sgmii specification ieee

    Abstract: vhdl code for frame synchronization sgmii sfp cyclone SFP sgmii altera IEEE 802.3 2002 ethernet phy sgmii vhdl code for phy interface sgmii SerDes sfp configuration fpga ethernet sgmii vhdl code CRC32
    Text: 10/100/1000 Ethernet MAC with SGMII Core Product Brief V1.0 - April 2004 1 Introduction Ethernet is available in different speeds 10/100/1000 and 10000Mbps and provides connectivity to meet a wide range of needs from desktop to switches. MorethanIP IP solutions


    Original     		10000Mbps) 10GbEth 100MbEth 10MbEth RFC2665, RFC2863, D-85757 sgmii specification ieee vhdl code for frame synchronization sgmii sfp cyclone SFP sgmii altera IEEE 802.3 2002 ethernet phy sgmii vhdl code for phy interface sgmii SerDes sfp configuration fpga ethernet sgmii vhdl code CRC32 PDF

    EMAC

    Abstract: MC9S12NE64 usb serial AN2692 HCS12 MC9S12NE64 MC9S12NE64-Family IEEE Standard 803.2 10Broad36 "controller area network" bus IEEE 802.3 Clause 4
    Text: Freescale Semiconductor Application Note AN2692 Rev. 0.2, 9/2004 MC9S12NE64 Integrated Ethernet Controller By Steven Torres 8/16 Bit System Engineering Austin, Texas Introduction Ethernet connectivity of embedded devices is a growing trend in industrial and consumer applications.


    Original     		AN2692 MC9S12NE64 EMAC MC9S12NE64 usb serial AN2692 HCS12 MC9S12NE64-Family IEEE Standard 803.2 10Broad36 "controller area network" bus IEEE 802.3 Clause 4 PDF

    verilog code for MII phy interface

    Abstract: MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4
    Text: PE-MACMII Dual-speed 10/100 Mbps Ethernet MAC March 11, 2002 Product Specification AllianceCORE Facts Alcatel Technology Leasing Group 11707 East Sprague, Suite 306 Spokane, WA 99206 Phone: +1 509-777-7604, +1 509-777-7330 Fax: +1 509-777-7006 [email protected]


    Original     		10Base-T 100Base-TX 100Base-FX 100Base-T4 16-bit verilog code for MII phy interface MII PHY verilog code for phy interface crc verilog code 16 bit ethernet mac verilog testbench vhdl code for phy interface 2V500FG456-4 PDF

    the RMII Consortium Specification

    Abstract: Mlt-3 LED1044 ST6179 4B5B decoder 842.21 ua 7809 10BT F840 LINK100
    Text: 84221 84221 Quad 100BaseTX/10BaseT Physical Layer Device PRELIMINARY 99191 Features Note: Check for latest Data Sheet revision before starting any designs. • Single Chip 100BaseTX/10BaseT Physical Layer Solution SEEQ Data Sheets are now on the Web, at www.lsilogic.com


    Original     		100BaseTX/10BaseT MD400184/A QQ84220 the RMII Consortium Specification Mlt-3 LED1044 ST6179 4B5B decoder 842.21 ua 7809 10BT F840 LINK100 PDF

    the RMII Consortium Specification

    Abstract: 4B5B decoder 84221 RMII Consortium
    Text: 84221 84221 Quad 100BaseTX/FX/10BaseT Physical Layer Device Technology Incorporated PRELIMINARY June 15, 1999 Note: Check for latest Data Sheet revision before starting any designs. Call SEEQ Technology 510 226-2903 —or— SEEQ Data Sheets are now on the Web, access


    Original     		100BaseTX/FX/10BaseT 100BaseTX/100BaseFX/10BaseT Base-TX/FX10 MD400184/­ QQ84220 the RMII Consortium Specification 4B5B decoder 84221 RMII Consortium PDF

    80225

    Abstract: NQ80225 LSI 80225 10BASET LINK100 LED VOLT RXCLK16
    Text: 80225 80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY 99025 Features Note: Check for latest Data Sheet revision before starting any designs. • Single Chip 100Base-TX /10Base-T Physical Layer Solution SEEQ Data Sheets are now on the Web, at


    Original     		MbpsTX/10BT 100Base-TX /10Base-T NQ80225 NQ80220 MD400182/A 80225 NQ80225 LSI 80225 10BASET LINK100 LED VOLT RXCLK16 PDF

    80225

    Abstract: LSI 80225 NQ80225 NQ80220 BT 816
    Text: 80225 80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY 99025 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access


    Original     		MbpsTX/10BT 100Base-TX /10Base-T NQ80225 NQ80220 MD400182/A 80225 LSI 80225 NQ80220 BT 816 PDF

    IP1000A

    Abstract: 93C46 LINK1000N LINK100N IP1000 1000Base-X 303112
    Text: IP1000A LF Preliminary Data Sheet Gigabit Ethernet NIC Single Chip – – – – – Features PCI & DMA Features – PCI Specification Revision 2.3 compliant – 32-bit, 33/66MHz bus master capability – Efficient DMA operation maximizes PCI band-width utilization


    Original     		IP1000A 32-bit, 33/66MHz 93C46 128-pin IP1000A LINK1000N LINK100N IP1000 1000Base-X 303112 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Gigabit Ethernet PCS IP Core for LatticeECP2M User’s Guide August 2007 ipug69_01.0 Gigabit Ethernet PCS IP Core for LatticeECP2M Lattice Semiconductor Introduction The 1000BASE-X physical layer, also referred to as the Gigabit Ethernet GbE physical layer, consists of three


    Original     		ipug69 1000BASE-X 8b10b LFE2M35E-5F672CES PDF

    L80225

    Abstract: HALO TG22-3506ND TG22-3506ND LINK100 ssd schematic l80225/b LSI L80225
    Text: L80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY Technical Manual Features • Single Chip 100Base-TX /10Base-T physical layer solution • On-chip wave shaping - no external filters required • Dual Speed - 10/100 Mbps • Baseline Wander Correction


    Original     		L80225 MbpsTX/10BT 100Base-TX /10Base-T MD400182/B HALO TG22-3506ND TG22-3506ND LINK100 ssd schematic l80225/b LSI L80225 PDF

    Untitled

    Abstract: No abstract text available
    Text: H General Description Features The DP83850C 100 Mb/s TX/T4 Repeater Interface Con­ troller, known as 100RIC, is designed specifically to meet the needs of today's high speed Ethernet networking sys­ tems. The DP83850C is fully compatible with the IEEE 802.3 repeater's clause 27.


    OCR Scan     		DP83850C 100RIC DP83850C 100RICTM) 100RIC, 100RIC 100BASE-TX PDF

    NQ80225

    Abstract: No abstract text available
    Text: 80225 Technology Incorporated 10/100 MbpsTX/10BT Ethernet Physical Layer Device PHY PRELIMINARY DATA SHEET Features • Single Chip 100Base-TX/10Base-T Physical Layer Solution U 3.3V Version of SEEQ 80221 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Dual Speed -10/100 Mbps


    OCR Scan     		MbpsTX/10BT 100Base-TX/10Base-T MD400182/A NQ80225 PDF

    Untitled

    Abstract: No abstract text available
    Text: 84221 LSI LOGIC Quad 100BaseTX/10BaseT Physical Layer Device PR ELIM INA R Y This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. 99191 Note: Check for latest Data Sheet revision before starting any designs.


    OCR Scan     		100BaseTX/10BaseT 100BaseTX 10BaseT MD400184/A PDF