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    INSTRUCTION SET PROCESSOR INTEL Search Results

    INSTRUCTION SET PROCESSOR INTEL Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation

    INSTRUCTION SET PROCESSOR INTEL Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    intel instruction set

    Abstract: 80960CA 80960SA reference opword branch conditional unconditional instruction
    Text: 1 Instruction Set Overview This chapter provides an overview of the i960 microprocessor family’s instruction set and i960 Jx processor-specific instruction set extensions. Also discussed are the assembly-language and instruction-encoding formats, various instruction groups and each group’s instructions.


    Original     		PDF

    bge 1,5

    Abstract: intel instruction set
    Text: Instruction Set Overview 5 This chapter provides an overview of the i960 microprocessor family’s instruction set and i960 RM/RN I/O processor-specific instruction set extensions. Also discussed are the assembly-language and instruction-encoding formats, various instruction groups and each group’s


    Original     		PDF

    ARM SC100 7816

    Abstract: ISO7816-2 AT91SC192192CT-USB ISO7816 ISO7816-3 LQFP64 SC100 6556a ARM SC100 Architecture inter chip usb
    Text: Features General • Based on the ARM SC100 SecureCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture


    Original     		PDF SC100TM 32-bit 16-bit 16-bit, 50MHz ISO7816-2 ARM SC100 7816 ISO7816-2 AT91SC192192CT-USB ISO7816 ISO7816-3 LQFP64 SC100 6556a ARM SC100 Architecture inter chip usb

    R80515 evatronix

    Abstract: 80515-like R80515 master-slave 8051 8 BIT ALU design with verilog code 80c31 code manual 80C517 80C31 80C51 80C515
    Text:  Eight-bit instruction decoder for MCS 51 instruction set  Executes instructions with one R8051XC Configurable 8-Bit Microcontroller Core The R8051XC is a configurable, single-chip, 8-bit microcontroller core that can imple® ment a variety of fast processor variations executing the MCS 51 instruction set.


    Original     		PDF R8051XC R8051XC 80C51. R8051XC-F R80515 evatronix 80515-like R80515 master-slave 8051 8 BIT ALU design with verilog code 80c31 code manual 80C517 80C31 80C51 80C515

    ARM SC100

    Abstract: ARM processor securecore ARM processor pin configuration ARM SC100 Architecture ARM SC100 7816 AT91SC512384RCT ISO7816-2 "flash controller" 7816 nand 6525a ISO7816-3
    Text: Features General • Based on the ARM SC100 SecureCore 32-bit RISC Processor • Two Instruction Sets • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture


    Original     		PDF SC100 32-bit 16-bit 16-bit, 50MHz ISO7816-2 ARM SC100 ARM processor securecore ARM processor pin configuration ARM SC100 Architecture ARM SC100 7816 AT91SC512384RCT ISO7816-2 "flash controller" 7816 nand 6525a ISO7816-3

    ARM SC100

    Abstract: ARM SC100 Architecture ARM SecurCore SC100 ARM pin configuration ARM processor based Circuit Diagram ARM SC100 7816 AT91SC25672RC SC100 32-bit microcontrollers atmel ARM processor data sheet
    Text: Features General • Based on the ARM SC100 SecurCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set 4-Gbyte Linear Address Space


    Original     		PDF SC100TM 32-bit 16-bit 16-bit, 1575CS ARM SC100 ARM SC100 Architecture ARM SecurCore SC100 ARM pin configuration ARM processor based Circuit Diagram ARM SC100 7816 AT91SC25672RC SC100 32-bit microcontrollers atmel ARM processor data sheet

    ARM SecurCore SC100

    Abstract: ARM SC100 ARM SC100 7816 AT91SC25672RC SC100 ARM SC100 Architecture java card ARM RNG
    Text: Features General • Based on the ARM SC100 SecurCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set 4-Gbyte Linear Address Space


    Original     		PDF SC100TM 32-bit 16-bit 16-bit, 1575AS ARM SecurCore SC100 ARM SC100 ARM SC100 7816 AT91SC25672RC SC100 ARM SC100 Architecture java card ARM RNG

    ARM SC100

    Abstract: ARM processor pin configuration ARM processor based Circuit Diagram ISO7816-2 AT91SC464384RCU ARM SC100 7816 AT91SC512384RCT CRC16 ISO7816-3 SC100
    Text: Features General • Based on the ARM SC100 SecureCore™ 32-bit RISC Processor • Two Instruction Sets • • • • • • • • • – ARM High-performance 32-bit Instruction Set – Thumb® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture


    Original     		PDF SC100TM 32-bit 16-bit 16-bit, 38MHz ISO7816-2 ARM SC100 ARM processor pin configuration ARM processor based Circuit Diagram ISO7816-2 AT91SC464384RCU ARM SC100 7816 AT91SC512384RCT CRC16 ISO7816-3 SC100

    EF86

    Abstract: NS486SXF CS16 NS486
    Text: Appendix A: Key Processor Differences from the ‘486 Appendix A: Key Processor Differences from the ‘486 The NS486SXF’s 32-bit processor is instruction set compatible with the standard Intel486 processor with the following exceptions: 1 NS486SXF operates in 16-bit and 32-bit protected


    Original     		PDF NS486SXF 32-bit Intel486 16-bit EF86 CS16 NS486

    LC1 D25 10

    Abstract: TMS320C80 LC1 D63 C8050 1994 AND sdram AND LC1 D38 AB32 AB34 0x0000B000 MP-124
    Text: TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023A – JULY 1994 – REVISED MARCH 1996 D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set


    Original     		PDF TMS320C80 SPRS023A 32-Bit IEEE-754 64-Bit 400M-Byte LC1 D25 10 TMS320C80 LC1 D63 C8050 1994 AND sdram AND LC1 D38 AB32 AB34 0x0000B000 MP-124

    DATA SHEET OF IC 317

    Abstract: MC9S08JM16 ic mn 15142 tem S08USBV1 74 series data book PID controller for Induction Motor control bhc capacitor HCS08 code example assembly universal motor data sheet HC08
    Text: MC9S08JM16 MC9S08JM8 Data Sheet HCS08 Microcontrollers MC9S08JM16 Rev. 2 5/2008 freescale.com MC9S08JM16 Series Features 8-Bit HCS08 Central Processor Unit CPU • • • • • 48 MHz HCS08 CPU (central processor unit) 24 MHz internal bus frequency HC08 instruction set with added BGND instruction


    Original     		PDF MC9S08JM16 MC9S08JM8 HCS08 MC9S08JM16 HCS08 DATA SHEET OF IC 317 ic mn 15142 tem S08USBV1 74 series data book PID controller for Induction Motor control bhc capacitor HCS08 code example assembly universal motor data sheet HC08

    MC9S08JM60

    Abstract: MC9S08JM60 c interrupt code example LQFP-48 thermal pad MC9S08JM32 PS2 Series connector S08USBV1 data sheet of temperature dependent resister MC9S08JM60 c code example PID controller for Induction Motor control HC08
    Text: MC9S08JM60 MC9S08JM32 Data Sheet HCS08 Microcontrollers MC9S08JM60 Rev. 3 1/2009 freescale.com MC9S08JM60 Series Features 8-Bit HCS08 Central Processor Unit CPU • • • • • 48-MHz HCS08 CPU (central processor unit) 24-MHz internal bus frequency HC08 instruction set with added BGND instruction


    Original     		PDF MC9S08JM60 MC9S08JM32 HCS08 MC9S08JM60 HCS08 48-MHz 24-MHz MC9S08JM60 c interrupt code example LQFP-48 thermal pad MC9S08JM32 PS2 Series connector S08USBV1 data sheet of temperature dependent resister MC9S08JM60 c code example PID controller for Induction Motor control HC08

    Untitled

    Abstract: No abstract text available
    Text: MC9S08JM60 MC9S08JM32 Data Sheet HCS08 Microcontrollers MC9S08JM60 Rev. 3 1/2009 freescale.com MC9S08JM60 Series Features 8-Bit HCS08 Central Processor Unit CPU • • • • • 48-MHz HCS08 CPU (central processor unit) 24-MHz internal bus frequency HC08 instruction set with added BGND instruction


    Original     		PDF MC9S08JM60 MC9S08JM32 HCS08 MC9S08JM60 HCS08 48-MHz 24-MHz

    S08USB

    Abstract: 256V0 HC08 HCS08 MC9S08JM32 MC9S08JM60 S08USBV1 MC9S08JM60 c code example freescale superflash
    Text: MC9S08JM60 MC9S08JM32 Data Sheet HCS08 Microcontrollers MC9S08JM60 Rev. 2 3/2008 freescale.com MC9S08JM60 Series Features 8-Bit HCS08 Central Processor Unit CPU • • • • • 48-MHz HCS08 CPU (central processor unit) 24-MHz internal bus frequency HC08 instruction set with added BGND instruction


    Original     		PDF MC9S08JM60 MC9S08JM32 HCS08 MC9S08JM60 HCS08 48-MHz 24-MHz S08USB 256V0 HC08 MC9S08JM32 S08USBV1 MC9S08JM60 c code example freescale superflash

    AB32

    Abstract: AB34 SM320C80 active aa33
    Text: SM320C80 DIGITAL SIGNAL PROCESSOR SGUS021 – AUGUST 1996 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set


    Original     		PDF SM320C80 SGUS021 32-Bit IEEE-754 64-Bit 400M-Byte AB32 AB34 SM320C80 active aa33

    C8050

    Abstract: No abstract text available
    Text: TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B - JULY 1994 - REVISED OCTOBER 1997 D Single-Chip Parallel Multiple D D D D D D D D D D D Instruction/Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) - 32-Bit Reduced Instruction Set


    Original     		PDF TMS320C80 SPRS023B 32-Bit IEEE-754 64-Bit 480M-Byte/s C8050

    LC1 D38

    Abstract: MIP 289 LC1 D25 004 LC1 D50 AB32 AB34 SM320C80 A1341
    Text: SM320C80 DIGITAL SIGNAL PROCESSOR SGUS021 – AUGUST 1996 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD DSP More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP) – 32-Bit Reduced Instruction Set


    Original     		PDF SM320C80 SGUS021 32-Bit IEEE-754 64-Bit 400M-Byte LC1 D38 MIP 289 LC1 D25 004 LC1 D50 AB32 AB34 SM320C80 A1341

    80960MC

    Abstract: branch conditional unconditional instruction
    Text: Instruction-Set Summary Q CHAPTER 6 INSTRUCTION-SET SUMMARY This chapter provides an overview of the instruction set for the 80960MC processor. Included is a discussion of the instruction format and a summary of the instruction groups and the instructions in each group.


    OCR Scan     		PDF 80960MC branch conditional unconditional instruction

    branch conditional unconditional instruction

    Abstract: i960 MC instruction
    Text: Instruction Set Summary 6 CHAPTER 6 INSTRUCTION SET SUMMARY This chapter provides an overview o f the instruction set for the i960 MC processor. Included is a discussion o f the instruction format and a summary of the instruction groups and the instructions in each group.


    OCR Scan     		PDF

    80960SA

    Abstract: 80960SB 80960
    Text: Instruction Set g CHAPTER 9 INSTRUCTION SET This chapter provides an overview of the instruction set for the 80960SA/SB processor. Included is a discussion of the instruction format, a summary of the instruction groups and the instructions in each group. This chapter gives detailed descriptions of each of the instructions. The instructions are listed


    OCR Scan     		PDF 80960SA/SB 80960SA 80960SB 80960

    Untitled

    Abstract: No abstract text available
    Text: intel APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers. It defines the processor status word PSW flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,


    OCR Scan     		PDF 80296SA

    4AM32

    Abstract: No abstract text available
    Text: SMJ320C80 DIGITAL SIGNAL PROCESSOR SG U S 0 2 5 - AUGUST 1998 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD Digital Signal Processor (DSP) • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set


    OCR Scan     		PDF SMJ320C80 32-Bit IEEE-754 64-Bit 4AM32

    Untitled

    Abstract: No abstract text available
    Text: i n y , APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers. It defines the processor status word PSW flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,


    OCR Scan     		PDF 4fl2bl75

    ic isl 887

    Abstract: T85 1e4 Switch TMS320C80 MP 1008 es MIP 289 C8050 AH-34 alu module for 32 bit processor GLC 555 texas instrument
    Text: TMS320C80 DIGITAL SIGNAL PROCESSOR S P R S Q 2 3 A -JULY 1994 - R E VIS ED MARCH 1996 • Single-Chip Parallel Multiple Instruction/Multiple Data MIMD DSP • More Than Two Billion RISC-Equivalent Operations per Second • Master Processor (MP) - 32-Bit Reduced Instruction Set


    OCR Scan     		PDF TMS320C80 SPRSQ23A-JULY 32-Bit IEEE-754 64-Bit 400M-Byte/s 4040035-3/D ic isl 887 T85 1e4 Switch TMS320C80 MP 1008 es MIP 289 C8050 AH-34 alu module for 32 bit processor GLC 555 texas instrument