JESD 51-7, ambient measurement
Abstract: scza005 SZZA013 JESD-51 dead bug
Text: Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs SZZA017A September 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest
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SZZA017A
SCZA005,
SZZA013,
JESD 51-7, ambient measurement
scza005
SZZA013
JESD-51
dead bug
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Untitled
Abstract: No abstract text available
Text: S i5 2111- B 3/ B 4 PCI-E XPRESS G EN 2 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 and Gen 2 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-B4
10-pin
Si52111-B3
Si52111-B5/B6
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Untitled
Abstract: No abstract text available
Text: S i 5 2 11 2 - B 5 / B 6 PCI-E XPRESS G EN 3 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-B6
10-pin
Si52112-B5
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Untitled
Abstract: No abstract text available
Text: S i 5 2 11 2 - A 1 / A 2 PCI-E XPRESS G EN 1 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-A2
10-pin
Si52112-A1
Si52112-B3/B4
Si52112-B5/B6
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Untitled
Abstract: No abstract text available
Text: S i5 2111- B 5/ B 6 PCI-E XPRESS G EN 3 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-B6
10-pin
Si52111-B5
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Untitled
Abstract: No abstract text available
Text: S i 5 2 11 2 - B 3 / B 4 PCI-E XPRESS G EN 2 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 and Gen 2 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-B4
10-pin
Si52112-B3
Si52112-B5/B6
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Untitled
Abstract: No abstract text available
Text: S i5 2111- A 1/ A 2 PCI-E XPRESS G EN 1 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-A2
10-pin
Si52111-A1
Si52111-B3/B4
Si52111-B5/B6
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SI52111B
Abstract: Si52111-B5
Text: S i5 2111- B 5/ B6 PCI-E XPRESS G EN 3 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-B6
10-pin
Si52111-B5
Si52111-B5/B6
SI52111B
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MO-229 footprint
Abstract: No abstract text available
Text: S i 5 2 11 2 - B 5 / B 6 PCI-E XPRESS G EN 3 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1, Gen 2, and Gen 3 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-B6
10-pin
Si52112-B5
MO-229 footprint
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Untitled
Abstract: No abstract text available
Text: S i 5 2 11 2 - B 3 / B 4 PCI-E XPRESS G EN 2 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 and Gen 2 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-B4
10-pin
Si52112-B3
Si52112-B5/B6
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si5211
Abstract: No abstract text available
Text: S i 5 2 11 2 - A 1 / A 2 PCI-E XPRESS G EN 1 DUAL O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 compliant Low power HCSL differential output buffers Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52112-A2
10-pin
Si52112-A1
Si52112-B3/B4
Si52112-B5/B6
si5211
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SI52111B
Abstract: No abstract text available
Text: S i5 2111- A 1/ A2 PCI-E XPRESS G EN 1 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-A2
10-pin
Si52111-A1
Si52111-B3/B4
Si52111-B5/B6
SI52111B
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SI52111-B4-GT
Abstract: No abstract text available
Text: S i5 2111- B 3/ B4 PCI-E XPRESS G EN 2 S INGLE O UTPUT C LOCK G ENERATOR Features PCI-Express Gen 1 and Gen 2 compliant Low power HCSL differential output buffer Supports Serial-ATA SATA at 100 MHz No termination resistors required
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Si52111-B4
10-pin
Si52111-B3
Si52111-B5/B6
SI52111-B4-GT
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CY2DP3110
Abstract: CY2DP3110AI CY2DP3110AIT MC100ES6111
Text: FastEdge Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Functional Description • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)
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CY2DP3110
32-pin
CY2DP3110
CY2DP3110AI
CY2DP3110AIT
MC100ES6111
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CY2PP3220
Abstract: CY2PP3220AI CY2PP3220AIT MC100ES6220
Text: FastEdge Series CY2PP3220 Dual 1:10 Differential Clock/Data Fanout Buffer Features Functional Description • Two sets of ten ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew
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CY2PP3220
52-pin
CY2PP3220
1-to-10
CY2PP3220AI
CY2PP3220AIT
MC100ES6220
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SZZA003
Abstract: thermal resistance of low power semiconductor
Text: Package Thermal Characterization Methodologies Application Report 1999 Printed in U.S.A 0399 SZZA003 Package Thermal Characterization Methodologies SZZA003 March 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products
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SZZA003
MIL-STD-883
SCAA022A
SZZA003
thermal resistance of low power semiconductor
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CY2DP3110
Abstract: CY2DP3110AI CY2DP3110AIT CY2DP3110AXIT MC100ES6111
Text: FastEdge Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Functional Description • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)
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CY2DP3110
32-pin
CY2DP3110
CY2DP3110AI
CY2DP3110AIT
CY2DP3110AXIT
MC100ES6111
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CY2DP314
Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314
Text: CY2DP314 1:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable
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CY2DP314
CY2DP314
CY2DP314OI
CY2DP314OIT
CY2DP314OXI
CY2DP314OXIT
P314
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CY2DP314
Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314
Text: CY2DP314 1:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable
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CY2DP314
CY2DP314
CY2DP314OI
CY2DP314OIT
CY2DP314OXI
CY2DP314OXIT
P314
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CY2DP314
Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314 13VAC
Text: CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable
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CY2DP314
CY2DP314
CY2DP314OI
CY2DP314OIT
CY2DP314OXI
CY2DP314OXIT
P314
13VAC
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56QN50T18080
Abstract: Senju MO-220-compliant Theta JA of 64-pin BGA 56RGQ senju solder paste MO-220 SN74SSTV16859 IPC-9701 qfn jc jb
Text: Application Report SCEA032 - March 2003 56-Pin Quad Flatpack No-Lead Logic Package Frank Mortan and Lance Wright SLL Package Development ABSTRACT Texas Instruments TI Quad Flatpack No-Lead (QFN) 56-terminal package complies with JEDEC standard MO-220, allows for board miniaturization, and holds several advantages
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SCEA032
56-Pin
56-terminal
MO-220,
56QN50T18080
Senju
MO-220-compliant
Theta JA of 64-pin BGA
56RGQ
senju solder paste
MO-220
SN74SSTV16859
IPC-9701
qfn jc jb
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8500A
Abstract: MC100ES6210 CY2PP318 CY2PP3210 CY2PP3210AI CY2PP3210AIT
Text: FastEdge Series CY2PP3210 Dual 1:5 Differential Clock/Data Fanout Buffer Features Functional Description • Dual sets of five ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew
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CY2PP3210
32-pin
MC100ES6210
CY2PP3210
8500A
MC100ES6210
CY2PP318
CY2PP3210AI
CY2PP3210AIT
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8500A
Abstract: Y2300 CY2PP318 CY2PP3210 CY2PP3210AI CY2PP3210AIT MC100ES6210
Text: FastEdge Series CY2PP3210 Dual 1:5 Differential Clock/Data Fanout Buffer Features Functional Description • Dual sets of five ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew
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CY2PP3210
32-pin
MC100ES6210
CY2PP3210
8500A
Y2300
CY2PP318
CY2PP3210AI
CY2PP3210AIT
MC100ES6210
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CY2DP3120
Abstract: CY2DP3120AI CY2DP3120AIT CY2DP3120AXI CY2DP3120AXIT MC100ES6221
Text: FastEdge Series CY2DP3120 1:20 Differential Fanout Buffer Features Functional Description The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The
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CY2DP3120
CY2DP3120
1-to-20
CY2DP3120AI
CY2DP3120AIT
CY2DP3120AXI
CY2DP3120AXIT
MC100ES6221
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