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    KM48S32230AT Search Results

    KM48S32230AT Datasheets (11)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    KM48S32230AT-F10 Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-F8 Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-FH Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-FL Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-G10 Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-G8 Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-G/F8 Samsung Electronics 8M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S32230AT-G/FA Samsung Electronics 8M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S32230AT-G/FL Samsung Electronics 8M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S32230AT-GH Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF
    KM48S32230AT-GL Samsung Electronics 8M x 8 Bit x 4 Banks Synchronous DRAM Scan PDF

    KM48S32230AT Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: PC100 Unbuffered DIMM KMM366S6453AT Revision History Revision 0.1 March 23, 1999 • Package dimension and Capacitance changed. Revision 0.2 (June 11, 1999) • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.


    Original     		PDF KMM366S6453AT PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: KMM374S3253ATS PC100 Unbuffered DIMM Revision History Revision 0.1 June 7, 1999 Package dimension and Capacitance changed. Revision 0.2 (July 5, 1999) • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.


    Original     		PDF KMM374S3253ATS PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: PC100 Unbuffered DIMM KMM366S3253ATS Revision History Revision 0.1 June 7, 1999 • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. • Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.


    Original     		PDF KMM366S3253ATS PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    KMM374S3253ATS-GA

    Abstract: No abstract text available
    Text: KMM374S3253ATS PC133 Unbuffered DIMM Revision History Revision 0.0 May, 1999 • PC133 first published. REV. 0 May 1999 KMM374S3253ATS PC133 Unbuffered DIMM KMM374S3253ATS SDRAM DIMM 32Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD


    Original     		PDF KMM374S3253ATS PC133 KMM374S3253ATS 32Mx72 32Mx8, KMM374S3253ATS-GA

    Untitled

    Abstract: No abstract text available
    Text: KMM374S3253ATS PC100 Unbuffered DIMM Revision History Revision 0.1 June 7, 1999 • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. • Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.


    Original     		PDF KMM374S3253ATS PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: KMM374S6453AT PC100 Unbuffered DIMM Revision History Revision 0.1 March 23, 1999 • Package dimension and Capacitance changed. Revision 0.2 (June 11, 1999) • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.


    Original     		PDF KMM374S6453AT PC100 118DIA 000DIA 19Min) 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: KM48S32230A CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 JUN 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 JUN 1999 KM48S32230A CMOS SDRAM Revision History Revision 0.1 Jan. 05, 1999


    Original     		PDF KM48S32230A 256Mbit A10/AP

    KMM366S924BTS

    Abstract: 64Mb samsung SDRAM pc133 sdram pc133 SDRAM DIMM KMM366S1723ATS-GA KMM374S823DTS-GA KM416S8030BT
    Text: PC133 Unbuffered DIMM SERIAL PRESENCE DETECT Unbuffered SDRAM DIMM 168pin PC133 4Layer SPD Specification REV. 0.2 Nov. 1999 REV. 0.2 Nov. 1999 PC133 Unbuffered DIMM SERIAL PRESENCE DETECT KMM366S823DTS-GA ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü Organization : 8Mx64


    Original     		PDF PC133 168pin) KMM366S823DTS-GA 8Mx64 KM48S8030DT-GA 375mil 4K/64ms 128byte KMM366S924BTS 64Mb samsung SDRAM pc133 sdram pc133 SDRAM DIMM KMM366S1723ATS-GA KMM374S823DTS-GA KM416S8030BT

    KMM366S3253TS-GA

    Abstract: No abstract text available
    Text: KMM366S3253ATS PC133 Unbuffered DIMM Revision History Revision 0.0 May., 1999 • PC133 first published. REV. 0 May 1999 KMM366S3253ATS PC133 Unbuffered DIMM KMM366S3253ATS SDRAM DIMM 32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD


    Original     		PDF KMM366S3253ATS PC133 KMM366S3253ATS 32Mx64 32Mx8, KMM366S3253TS-GA

    RA12

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S32230A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 8 x 8,392,608 words by 8 bits,


    Original     		PDF KM48S32230A KM48S32230A A10/AP RA12

    RA12

    Abstract: No abstract text available
    Text: KM48S32230A Preliminary PC133 CMOS SDRAM Revision History Revision 0.0 Jan., 1999 • PC133 first published. REV. 0 Jan. '99 Preliminary PC133 CMOS SDRAM KM48S32230A 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply


    Original     		PDF KM48S32230A PC133 KM48S32230A A10/AP RA12

    Untitled

    Abstract: No abstract text available
    Text: PC100 Unbuffered DIMM KMM366S6453AT Revision History Revision 0.1 March 23, 1999 • Package dimension and Capacitance changed. Revision 0.2 (June 11, 1999) • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.


    Original     		PDF KMM366S6453AT PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: KMM374S6453AT PC100 Unbuffered DIMM Revision History Revision 0.1 March 23, 1999 • Package dimension and Capacitance changed. Revision 0.2 (June 11, 1999) • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.


    Original     		PDF KMM374S6453AT PC100 118DIA 000DIA 19Min) 32Mx8 KM48S32230AT

    Untitled

    Abstract: No abstract text available
    Text: PC100 Unbuffered DIMM KMM366S3253ATS Revision History Revision 0.1 June 7, 1999 • Skip ICC4 value of CL=2 in DC characteristics in datasheet. • Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER. • Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.


    Original     		PDF KMM366S3253ATS PC100 118DIA 000DIA 32Mx8 KM48S32230AT

    B1A12

    Abstract: KMM377S6453AT-GH
    Text: KMM377S6453AT SDRAM MODULE KMM377S6453AT SDRAM DIMM 64Mx72 SDRAM DIMM with PLL & Register based on 32Mx8, 4Banks 8K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM377S6453AT is a 64M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM377S6453AT consists of eighteen CMOS 32Mx8 bit


    Original     		PDF KMM377S6453AT KMM377S6453AT 64Mx72 32Mx8, 32Mx8 400mil 18bits 168-pin B1A12 KMM377S6453AT-GH

    Untitled

    Abstract: No abstract text available
    Text: KMM366S6453AT PC100 SDRAM MODULE KMM366S6453AT SDRAM DIMM 64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM366S6453AT is a 64M bit x 64 Synchronous • Performance range Dynamic RAM high density memory module. The Samsung


    OCR Scan     		PDF KMM366S6453AT KMM366S6453AT PC100 64Mx64 32Mx8, 400mil 168-pin

    Untitled

    Abstract: No abstract text available
    Text: PC100 SDRAM MODULE KMM374S3253ATS KMM374S3253ATS SDRAM DIMM 32Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM374S3253ATS is a 32M bit x 72 Synchro­ • Performance range


    OCR Scan     		PDF PC100 KMM374S3253ATS KMM374S3253ATS 32Mx72 32Mx8, 400mil 168-pin

    Untitled

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M X 8Bit X 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S32230A is 268,435,456 bits synchronous high data • LVTTL compatible with multiplexed address rate Dynamic RAM organized as 8 x 8,392,608 words by 8 bits,


    OCR Scan     		PDF KM48S32230A KM48S32230A

    Untitled

    Abstract: No abstract text available
    Text: KMM374S3253AT PC100 SDRAM MODULE KMM374S3253AT SDRAM DIMM 32Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD FEATURE GENERAL DESCRIPTION The Samsung KMM374S3253AT is a 32M bit x 72 Synchro­ • Performance range


    OCR Scan     		PDF KMM374S3253AT KMM374S3253AT PC100 32Mx72 32Mx8, 400mil 168-pin

    Untitled

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S32230A 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM48S32230A is 268,435,456 bits synchronous high data • LVTTL compatible with multiplexed address rate Dynamic RAM organized as 8 x 8,392,608 words by 8 bits,


    OCR Scan     		PDF KM48S32230A KM48S32230A 10/AP

    Untitled

    Abstract: No abstract text available
    Text: KMM366S3253AT PC100 SDRAM MODULE KMM366S3253AT SDRAM DIMM 32Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD FEATURE GENERAL DESCRIPTION The Samsung KMM366S3253AT is a 32M bit x 64 Synchro­ • Performance range nous Dynamic RAM high density memory module. The Sam ­


    OCR Scan     		PDF KMM366S3253AT PC100 KMM366S3253AT 32Mx64 32Mx8, M366S3253AT-G8 125MHz 400mil

    Untitled

    Abstract: No abstract text available
    Text: KMM374S3253AT PC100 SDRAM MODULE KMM374S3253AT SDRAM DIMM 32Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD FEATURE GENERAL DESCRIPTION The Samsung KMM374S3253AT is a 32M bit x 72 Synchro­ • Performance range


    OCR Scan     		PDF KMM374S3253AT PC100 KMM374S3253AT 32Mx72 32Mx8, M374S3253AT-G8 100MHz KMM374S3253AT-GL 168-pin

    km48s2020ct

    Abstract: S823B 4MX16 54-PIN u108h KM48S2020 44s16030
    Text: General Information CMOS DRAM A. Product Guide Component Density 16M 4th Part Number Org. KM44S4020CT 4Mx4 KM48S2020CT 2Mx8 KM416S1020CT 1Mx16 KM416S1021CT Speed G F *2 Package Avail. (TSOPII) LVTTL 4K 3.3 ±0.3 S/t-P/L/IO 8/H/L/10 44pin C/S c/s 2 Banks


    OCR Scan     		PDF KM44S4020CT KM48S2020CT KM416S1020CT KM416S1021CT KM44S16020BT KM48S8020BT KM416S4020BT KM416S4021BT KM44S160308T KM48S8030BT S823B 4MX16 54-PIN u108h KM48S2020 44s16030

    Untitled

    Abstract: No abstract text available
    Text: KMM366S6453AT PC100 SDRAM MODULE KMM366S6453AT SDRAM DIMM 64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM366S6453AT is a 64M bit x 64 Synchronous • Performance range Dynamic RAM high density memory module. The Samsung


    OCR Scan     		PDF KMM366S6453AT PC100 KMM366S6453AT 64Mx64 32Mx8, M366S6453AT-G8 125MHz 400mil