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    74LS76AP

    Abstract: LS 74LS76ap M74LS76AP T flip flop pin configuration
    Text: M ITSUBISHI L S T T L s M74LS76AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH S E T AND R ES E T DESCRIPTION The M 7 4L S 76 A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing 2 J-K negative edge-triggered flip -flo p circuits


    OCR Scan     		PDF M74LS76AP M74LS76AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS76AP LS 74LS76ap T flip flop pin configuration