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    M74LS12P Search Results

    M74LS12P Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    M74LS12P Mitsubishi Triple 3-Input Positive NAND Gate with Open Collector Output Original PDF
    M74LS12P Unknown TTL Data Book 1980 Scan PDF

    M74LS12P Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    M74LS12P

    Abstract: 74LS12P 20-PIN
    Text: MITSUBISHI LSTTLs M 7 4 LS1 2 P T R IP L E 3-INPUT P O SITIV E NAND GATE WITH OPEN CO LLECTO R OUTPUT DESCRIPTION The M74LS12P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing three triple-input positive-logic NAND gates with open collector outputs, usable as negative-logic NOR


    OCR Scan     		M74LS12P M74LS12P 500ns, 50ffc. b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS12P PDF

    74LS12P

    Abstract: No abstract text available
    Text: MITSUBISHI LSTTLs M 7 4 LS1 2 P T R IP L E 3-INPUT P O SITIV E NAND GATE WITH OPEN CO LLECTO R OUTPUT DESCRIPTION The M74LS12P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing three triple-input positive-logic NAND gates with open collector outputs, usable as negative-logic NOR


    OCR Scan     		M74LS12P 50ffc. b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS12P PDF