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    MARKING CODE VM SOT35 Search Results

    MARKING CODE VM SOT35 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54LS42/BEA Rochester Electronics LLC 54LS42 - DECODER, BCD-TO-DECIMAL - Dual marked (M38510/30703BEA) Visit Rochester Electronics LLC Buy
    5446/BEA Rochester Electronics LLC 5446 - Decoder, BCD-To-7-Segment, With Open-Collector Outputs - Dual marked (M38510/01006BEA) Visit Rochester Electronics LLC Buy
    5447/BEA Rochester Electronics LLC 5447 - Decoder, BCD-To-7-Segment, With Open-Collector Outputs - Dual marked (M38510/01007BEA) Visit Rochester Electronics LLC Buy
    MG8097/B Rochester Electronics LLC 8097 - Math Coprocessor - Dual marked (8506301ZA) Visit Rochester Electronics LLC Buy
    5490/BCA Rochester Electronics LLC 5490 - Decade Counter - Dual marked (M38510/01307BCA) Visit Rochester Electronics LLC Buy

    MARKING CODE VM SOT35 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    74abt374 Philips

    Abstract: MARKING CODE SMD IC 531
    Text: INTEGRATED CIRCUITS 74ABT646A Octal bus transceiver/register 3-State Product specification Supersedes data of 1995 Sep 06 IC23 Data Handbook Philips Semiconductors 1998 Feb 17 Philips Semiconductors Product specification Octal bus transceiver/register (3-State)


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    74ABT646A 74ABT646A 74ABT245 74ABT374 500mA 01-Jan-98) 74abt374 Philips MARKING CODE SMD IC 531 PDF

    SA00215

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS 74ABT657 Octal transceiver with parity generator/checker 3-State Product specification IC23 Data Handbook Philips Semiconductors 1995 Dec 11 Philips Semiconductors Product specification Octal transceiver with parity generator/checker


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    74ABT657 74ABT657 500mA 01-Jan-98) SA00215 PDF

    XC7SET125GV

    Abstract: JESD22-A114E MO-203 XC7SET125
    Text: XC7SET125 Bus buffer/line driver; 3-state Rev. 01 — 4 September 2009 Product data sheet 1. General description XC7SET125 is a high-speed Si-gate CMOS devices. It provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable


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    XC7SET125 XC7SET125 OT353-1 OT753 JESD22-A114E: JESD22-A115-A: JESD22-C101C: XC7SET125GV JESD22-A114E MO-203 PDF

    sot753 marking 13

    Abstract: JESD22-A114E MO-203 XC7SH125GV XC7SH125
    Text: XC7SH125 Bus buffer/line driver; 3-state Rev. 01 — 4 September 2009 Product data sheet 1. General description XC7SH125 is a high-speed Si-gate CMOS device. It provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE .


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    XC7SH125 XC7SH125 OT353-1, OT753, OT886, OT891 JESD22-A114E: JESD22-A115-A: JESD22-C101C: sot753 marking 13 JESD22-A114E MO-203 XC7SH125GV PDF

    Untitled

    Abstract: No abstract text available
    Text: 74HC1G125-Q100; 74HCT1G125-Q100 Bus buffer/line driver; 3-state Rev. 1 — 18 June 2013 Product data sheet 1. General description The 74HC1G125-Q100; 74HCT1G125-Q100 is a single buffer/line driver with 3-state output. Inputs include clamp diodes. This enables the use of current limiting resistors to


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    74HC1G125-Q100; 74HCT1G125-Q100 74HCT1G125-Q100 AEC-Q100 74HC1G125-Q100: HCT1G125 PDF

    JESD87

    Abstract: v25 sot353 VM MARKING CODE SOT353 74LVC1G125GV AN10161
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC1G125 Bus buffer/line driver; 3-state Product specification Supersedes data of 2002 May 28 2002 Nov 18 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V


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    74LVC1G125 JESD8B/JESD36 EIA/JESD22-A114-A EIA/JESD22-A115-A 01-Nov-02) JESD87 v25 sot353 VM MARKING CODE SOT353 74LVC1G125GV AN10161 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 10 — 7 December 2011 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE


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    74LVC1G125 74LVC1G125 PDF

    JESD22-A114E

    Abstract: MO-203 XC7SET86GV
    Text: XC7SET86 2-input EXCLUSIVE-OR gate Rev. 01 — 7 September 2009 Product data sheet 1. General description XC7SET86 is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. 2. Features • Symmetrical output impedance ■ High noise immunity


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    XC7SET86 XC7SET86 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SET86GW JESD22-A114E MO-203 XC7SET86GV PDF

    74LVC1G125

    Abstract: 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV 74LVC1G125GW JESD22-A114-F SOT353-1 74LVC1G125GS
    Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 9 — 29 December 2010 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE


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    74LVC1G125 74LVC1G125 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV 74LVC1G125GW JESD22-A114-F SOT353-1 74LVC1G125GS PDF

    SOT753

    Abstract: JESD22-A114E MO-203
    Text: XC7SH86 2-input EXCLUSIVE-OR gate Rev. 01 — 7 September 2009 Product data sheet 1. General description XC7SH86 is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. 2. Features • Symmetrical output impedance ■ High noise immunity


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    XC7SH86 XC7SH86 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SH86GW SOT753 JESD22-A114E MO-203 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7SET32 2-input OR gate Rev. 01 — 3 September 2009 Product data sheet 1. General description XC7SET32 is a high-speed Si-gate CMOS device. It provides a 2-input OR function. 2. Features • Symmetrical output impedance ■ High noise immunity ■ ESD protection:


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    XC7SET32 XC7SET32 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SET32GW PDF

    sot753

    Abstract: sot753 marking 13 JESD22-A114E MO-203
    Text: XC7SET32 2-input OR gate Rev. 01 — 3 September 2009 Product data sheet 1. General description XC7SET32 is a high-speed Si-gate CMOS device. It provides a 2-input OR function. 2. Features • Symmetrical output impedance ■ High noise immunity ■ ESD protection:


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    XC7SET32 XC7SET32 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SET32GW sot753 sot753 marking 13 JESD22-A114E MO-203 PDF

    JESD22-A114E

    Abstract: MO-203
    Text: XC7SH32 2-input OR gate Rev. 01 — 2 September 2009 Product data sheet 1. General description XC7SH32 is a high-speed Si-gate CMOS device. It provides a 2-input OR function. 2. Features • Symmetrical output impedance ■ High noise immunity ■ ESD protection:


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    XC7SH32 XC7SH32 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SH32GW JESD22-A114E MO-203 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7SET86 2-input EXCLUSIVE-OR gate Rev. 01 — 7 September 2009 Product data sheet 1. General description XC7SET86 is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. 2. Features • Symmetrical output impedance ■ High noise immunity


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    XC7SET86 XC7SET86 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 XC7SET86GW PDF

    74LVC1G125GW

    Abstract: 74LVC1G125 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353
    Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 8 — 24 August 2010 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE


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    74LVC1G125 74LVC1G125 74LVC1G125GW 74LVC1G125GF 74LVC1G125GM 74LVC1G125GV VM MARKING CODE SOT353 PDF

    JESD78

    Abstract: 74CBTLV1G125 74CBTLV1G125GM 74CBTLV1G125GV 74CBTLV1G125GW
    Text: 74CBTLV1G125 Single bus switch Rev. 2 — 29 July 2010 Product data sheet 1. General description The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled when the output enable OE input is high. To ensure the high-impedance OFF-state during power up or power down, OE should be


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    74CBTLV1G125 74CBTLV1G125 JESD78 74CBTLV1G125GM 74CBTLV1G125GV 74CBTLV1G125GW PDF

    Untitled

    Abstract: No abstract text available
    Text: 74CBTLV1G125 Single bus switch Rev. 3 — 15 December 2011 Product data sheet 1. General description The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled when the output enable OE input is high. To ensure the high-impedance OFF-state during power up or power down, OE should be


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    74CBTLV1G125 74CBTLV1G125 PDF

    sot355

    Abstract: hct154 74HC154N
    Text: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT154


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    74HC/HCT/HCU/HCMOS 74HC/HCT154 4-to-16 16-line 01-Nov-97) sot355 hct154 74HC154N PDF

    74AHC1G126GV

    Abstract: 74AHC1G126 74AHC1G126GW 74AHCT1G126 74AHCT1G126GV 74AHCT1G126GW JESD22-A114E AHC* marking
    Text: 74AHC1G126; 74AHCT1G126 Bus buffer/line driver; 3-state Rev. 07 — 17 June 2009 Product data sheet 1. General description 74AHC1G126 and 74AHCT1G126 are high-speed Si-gate CMOS devices. They provide one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by


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    74AHC1G126; 74AHCT1G126 74AHC1G126 74AHCT1G126 AHCT1G126 74AHC1G126GV 74AHC1G126GW 74AHCT1G126GV 74AHCT1G126GW JESD22-A114E AHC* marking PDF

    V6 marking code

    Abstract: 74LVC1G125GM
    Text: 74LVC1G125 Bus buffer/line driver; 3-state Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input OE . A HIGH-level at pin OE


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    74LVC1G125 74LVC1G125 V6 marking code 74LVC1G125GM PDF

    v08 smd marking code

    Abstract: NXP date code marking nxp Standard Marking SOT1202 SOT1115 marking nxp package 74LVC1G08GW
    Text: 74LVC1G08 Single 2-input AND gate Rev. 8 — 19 October 2010 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


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    74LVC1G08 74LVC1G08 OT886 74LVC1G08GM OT353-1 74LVC1G08GW v08 smd marking code NXP date code marking nxp Standard Marking SOT1202 SOT1115 marking nxp package PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments Top View The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V


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    74LVC1G00 74LVC1G00 OT553 DS32196 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7SET14 Inverting Schmitt trigger Rev. 01 — 31 August 2009 Product data sheet 1. General description XC7SET14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input


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    XC7SET14 XC7SET14 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 PDF

    JESD22-A114E

    Abstract: MO-203 XC7SET14 XC7SET14GW
    Text: XC7SET14 Inverting Schmitt trigger Rev. 01 — 31 August 2009 Product data sheet 1. General description XC7SET14 is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This device is capable of transforming slowly changing input


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    XC7SET14 XC7SET14 JESD22-A114E: JESD22-A115-A: JESD22-C101C: OT353-1 OT753 JESD22-A114E MO-203 XC7SET14GW PDF