21064A-200
Abstract: 21064A-233 21064A-275 21064A-275-PC 21064A-300 pfn 109 06f irf 4110 M23VDD gh11
Text: Alpha 21064A Microprocessors Data Sheet Order Number: EC–QFGKC–TE This document contains information about the following Alpha microprocessors: 21064A–200, 21064A–233, 21064A–275, 21064A–275–PC, and 21064A–300. Revision/Update Information:
|
Original
|
1064A
N0301
N0107
N0567
21064A-200
21064A-233
21064A-275
21064A-275-PC
21064A-300
pfn 109 06f
irf 4110
M23VDD
gh11
|
PDF
|
ARM9TDMI
Abstract: ARM922T 141 mrc basic architecture of ARM Processors B-30 CP15
Text: ARM922T Rev 0 Technical Reference Manual Copyright 2000, 2001 ARM Limited. All rights reserved. ARM DDI 0184B ARM922T Technical Reference Manual Copyright © 2000, 2001 ARM Limited. All rights reserved. Release Information Change history Date Issue Change
|
Original
|
ARM922T
0184B
ARM9TDMI
ARM922T
141 mrc
basic architecture of ARM Processors
B-30
CP15
|
PDF
|
AXP 188 ba
Abstract: 21071-DA 2mb1100 AXP 188 IC 5188b RSAD 5111 1M 21071-BA 82378IB 21071AA d327c
Text: m DECchip 21071-AA, 21072-AA Core Logic Data Sheet m A p ril 1994 21071-AA, 21072-A A Features: • Supports the entire fam ily of the DECchip 21064 Alpha AXP m icroprocessors • DECchip 21071-AA: 128-bit cache/64-bit memory • DECchip 21072-AA: 128-bit cache/128-bit
|
OCR Scan
|
21071-AA,
1072-A
128-bit
cache/64-bit
21072-AA:
cache/128-bit
32-bit
parity/32-bit
21072-AA
AXP 188 ba
21071-DA
2mb1100
AXP 188 IC
5188b
RSAD 5111 1M
21071-BA
82378IB
21071AA
d327c
|
PDF
|
R3051
Abstract: R3001
Text: Data Book C, Section 5.5, Page 1 IDT79R3051/3051E/3052/3052E IDT79R3051 FAMILY OF INTEGRATED RISControllers PRELIMINARY IDT 79R3051™, 79R3051E IDT 79R3052™, 79R3052E In teg rated D evice T echnology, Inc. FEATURES: — On-chip DMA arbiter — Bus Interface M inimizes Design Complexity
|
OCR Scan
|
IDT79R3051/3051E/3052/3052E
IDT79R3051
79R3051â
79R3051E
79R3052â
79R3052E
R3720/21/22
84-pin
79R3051
3051E
R3051
R3001
|
PDF
|
Untitled
Abstract: No abstract text available
Text: i:WNp J READ INTERFACE CHAPTER 8 d t I n t e g r a t e d D € v iz e T e c h n o lo g y , l i e . INTRODUCTION The R3041 read protocol h a s b een designed to interface to a wide variety of m em ory a n d I/O devices. P articu lar care h a s b e e n ta k e n in th e definition of
|
OCR Scan
|
R3041
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MB86833 SPARCIite SERIES 32-BIT RISC EMBEDDED PROCESSOR FUJITSU DATASHEET MARCH 1998 FEATURES Programmable address decoder and wait-state genera tor Single vector trapping • 66 M Hz CPU with on-chip clock multiplier 0.35 micron gate, 2-level metal CMOS technology,
|
OCR Scan
|
MB86833
32-BIT
B86833
MB8683X
FPT-144P-M08)
144-LEAD
|
PDF
|
R3000-T
Abstract: No abstract text available
Text: i :Sï¥NN^ | IDT79R3071 IDT79R3071E IDT79R3071 RISController™ d t In tegrated Devize T echnology, Inc. FEATURES Large on-chip caches with user configurability — 16kB Instruction Cache, 4kB Data Cache — Dynamically configurable to 8kB Instruction
|
OCR Scan
|
IDT79R3071TM
IDT79R3071
IDT79R3071E
84-pin
R3000-T
|
PDF
|
eerl
Abstract: ym oca QQ11
Text: INTEGRATE» DEVICE SflE D • 4025771 R3081 BLOCK DIAGRAM BrCond 3:2,0 C lock G enerator Unit/ C lock Doubler M aster Pipeline Control System Control C oprocessor Integer CPU Core Floating Point C oprocessor (CP1) (CP0) Exception/Control Registers G eneral Registers
|
OCR Scan
|
0D112fa7
IDT79R3081
79R3081TM,
79R3081E
79R3081L,
79R3081LE
R301OA
84-Pln
84-Pin
79R3081
eerl
ym oca
QQ11
|
PDF
|
C 5271 manual
Abstract: No abstract text available
Text: QED RISCMark RM5271™ 64-Bit Superscalar Microprocessor FEATURES: • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle — 200, 225, 250, 266 M H z op era ting frequ en cies — 345 D hrystone, 2.1 M IP S m axim um
|
OCR Scan
|
RM5271TM
64-Bit
R4600,
R4700
R5000
10OOMBps
64-bitm
DS-5271,
C 5271 manual
|
PDF
|
AMD K6
Abstract: No abstract text available
Text: Preliminary Information AMDB AMD-K6-2E Embedded Processor Data Sheet Publication # 22529 Issue Date: Jan 2000 Rev: B Amendment/0 2000 Advanced Micro Devices, Inc. All rights reserved. T h e c o n te n ts of th is d o c u m e n t a r e p ro v id e d in co n n e c tio n w ith A d v a n c e d M icro
|
OCR Scan
|
AMD-K6-2E/350AFR
321-pin
AMD-K6-2E/333AFR
AMD-K6-2E/300AFR
AMD-K6-2E/266AFR
AMD-K6-2E/233AFR
AMD K6
|
PDF
|
82C801
Abstract: 486DLC/IBM opti 486 chipset
Text: E ili iìj é u n SAHJU 82C802GP System/Power Management Controller 1.0 • Features - Supports CPUs with L1 write-back feature Processor interface: - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D • - AMD® 486DX, DX2, DXL, DXL2, Plus - Cyrix® DX, DX2, M7
|
OCR Scan
|
82C802GP
80486SX,
486DX,
50MHz
33MHz
82C801
486DLC/IBM
opti 486 chipset
|
PDF
|
MN871107
Abstract: 04A05 MN5520A
Text: For Information Equipment Panasonic MN5520A Low Power CPU-Controller for PC/AT Computers • Overview The MN5520A is a CPU controller. It is designed for use in combination with the MN5521 I/O peripheral controller and the MN871107 floppy disk drive controller in notebook,
|
OCR Scan
|
MN5520A
MN5521
MN871107
MN5520A
486SX/DX/
04A05
|
PDF
|
9042h
Abstract: DRB102
Text: SLC90E42 ADVANCE INFORMATION STANDARD MICROSYSTEMS CORPORATION SLC90E42 NorthBridge Member of High Performance TeXas Chipset FE A TU R E S 324 Pin BGA North Bridge Chip Supports the Pentium Compatible Processor with Host Bus from 60 MHz to 75 MHz at 3.3V and
|
OCR Scan
|
SLC90E42
SLC90E42
64Mbit
9042h
DRB102
|
PDF
|
supersparc
Abstract: HY 1021A Sun STP1021 3AR3 cap 220 htz ADA33
Text: [ f ^ T l r í A C K j S un M i c r o e l e c t r o n i c s July 1997 SuperSPARC“-ll DATA SHEET SPARC v8 32-Bit Superscalar Microprocessor D e s c r ip t io n The STP1021A is a new m em ber of the Su p erSPA R C T I fam ily o f m icroprocessor products. L ik e its predeces
|
OCR Scan
|
STP1021A
STP1020N,
STP1020
STP1021)
cl277
data12
STP1021APGA-85
STP1021APGA-75
supersparc
HY 1021A
Sun STP1021
3AR3
cap 220 htz
ADA33
|
PDF
|
|
|
CHE 6100
Abstract: No abstract text available
Text: QED RISCMark RM7000™ 64-Bit Superscalar Microprocessor Advanced Information FEATURES: • RM 5270 and RM5271 pin com patible • Dual Issue s ym m e tric su p e rsca la r m icro p ro ce sso r w ith in stru c tion prefetch op tim ize d for system level p rice/pe rfo rm ance
|
OCR Scan
|
RM7000TM
64-Bit
RM5271
int95
DS-7000,
CHE 6100
|
PDF
|
MIPS R3051
Abstract: No abstract text available
Text: Integrated Device Technology, Inc. Single, double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls On-chip 4-word read buffer supports burst or simple block
|
OCR Scan
|
67MHz,
20MHz,
25MHz
33MHz
20MIPS
25MHz
84-pin
24-bit
16-bit,
32-bit
MIPS R3051
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 6. ELECTRICAL SPECIFICATIONS Thermal forced is condition: In terms of air cooling is resumed. required under pertinent temperature Forced air, the worst conditions. characteristics, of at least 1.5m/s, This ma y depend on the conditions. Ab s o l u t e maximum ratings
|
OCR Scan
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SLC90E42 ADVANCE INFORMATION STANDARD MICROSYSTEMS CORPORATION SLC90E42 NorthBridge Member of High Performance TeXas Chipset FEATURES 324 Pin BGA North Bridge Chip Supports the Pentium C om patible Processor with Host Bus from 60 MHz to 75 MHz at 3.3V and
|
OCR Scan
|
SLC90E42
SLC90E42
|
PDF
|
5650300
Abstract: XXXW
Text: QED RISCMark RM5231™ 64-Bit Superscalar Microprocessor FEATURES: • Pinout com p atib le w ith po pu lar R M 5230 w ith split po w e r s u p plies 2.5V and 3.3V • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle
|
OCR Scan
|
RM5231TM
64-Bit
DS-5231,
5650300
XXXW
|
PDF
|
RM5260
Abstract: No abstract text available
Text: QED RISCMark RM5260™ 64-Bit Superscalar Microprocessor FEATURES: • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle — 133, 150, 175 and 200 M Hz opera ting fre q u e n cy — 260 Dhrystone2.1 M IPS
|
OCR Scan
|
RM5260TM
64-Bit
R4600,
R4700
R5000
S-5260,
RM5260
|
PDF
|
40XX
Abstract: V4700TM
Text: IDT79R 47 00 IDT79R V4700™ 64-BIT RISC M IC R O P R O C E S S O R • FEATURES • True 64-bit microprocessor - 64-bit integer operations - 64-bit floating-point operations - 64-bit registers - 64-bit virtual address space • High-performance microprocessor
|
OCR Scan
|
64-BIT
IDT79R
V4700TM
200MHz
40XX
V4700TM
|
PDF
|
21071-AA
Abstract: ysd 2-11 invr 054
Text: m DECchip 21071-AA, 21072-AA Core Logic Data Sheet m A p ril 1994 21071-AA, 21072-A A Features: • Supports the entire fam ily of the DECchip 21064 Alpha AXP m icroprocessors • DECchip 21071-AA: 128-bit cache/64-bit memory • DECchip 21072-AA: 128-bit cache/128-bit
|
OCR Scan
|
21071-AA,
21072-AA
1072-A
21071-AA:
128-bit
cache/64-bit
21072-AA:
cache/128-bit
21071-AA
ysd 2-11
invr 054
|
PDF
|
STR 6252 equivalent
Abstract: No abstract text available
Text: ARM610 Data Sheet ARM610 RISC Processor ARM610 is a general purpose 32-bit microprocessor with 4kByte cache, W rite Buffer and Memory M anagement Unit MMU combined in a single chip. The ARM610 offers a high level of RISC performance yet it's fully static design ensures minimal pow er consumption - m aking it ideal for portable, battery
|
OCR Scan
|
ARM610
32-bit
P610ARM
STR 6252 equivalent
|
PDF
|
Untitled
Abstract: No abstract text available
Text: C h apter 3 MB86831 Bus Interface Unit 3.1 Overview of Bus Interface Unit The BIU on the MB86831 offers the following features: • Option to run core at multiplied frequency of the Bus Interface Unit, xl, x2, x3, x4. • Four-word burst mode for instruction fetches and data loads,
|
OCR Scan
|
MB86831
MB86831
|
PDF
|