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    Plessey Semiconductors Ltd PDSP16112/PG

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    PDSP161 Datasheets (64)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    PDSP1610 Unknown Shortform IC and Component Datasheets (Plus Cross Reference Data) Short Form PDF
    PDSP16112 Zarlink Semiconductor 16 x 12 Bit Complex Multiplier Original PDF
    PDSP16112 Unknown Shortform IC and Component Datasheets (Plus Cross Reference Data) Short Form PDF
    PDSP16112A Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112/A0/AC Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112A0AC Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112A0AC GEC Plessey Semiconductors 16 x 12 BIT COMPLEX MULTIPLIER Scan PDF
    PDSP16112A/A0/AC Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112AA0AC Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112A/A0/GG Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112AA0GG Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112A/B0/AC Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112AB0AC Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112AB0AC GEC Plessey Semiconductors 16 x 12 BIT COMPLEX MULTIPLIER Scan PDF
    PDSP16112A/B0/GG Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112AB0GG Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112A/C0/AC Zarlink Semiconductor Logic ICS, 16x12 Bit Complex Muliplier Original PDF
    PDSP16112AC0AC Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF
    PDSP16112A C0 GG Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLEXER Original PDF
    PDSP16112AC0GG Zarlink Semiconductor 16 x 12 BIT COMPLEX MULTIPLIER Original PDF

    PDSP161 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    AN59

    Abstract: PDSP1601 PDSP16116 PDSP16116A PDSP16318 Application of dsp in sonar for m.sc i-C4H10
    Text: AN59 A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A has been designed with an integral Block Floating Point system which can be used, in conjunction with other Zarlink Semiconductor PDSP parts, to process FFTs with a combination of speed and accuracy previously unobtainable. All the


    Original     		PDSP16116A 20MHz 259us 118us AN59 PDSP1601 PDSP16116 PDSP16318 Application of dsp in sonar for m.sc i-C4H10 PDF

    Untitled

    Abstract: No abstract text available
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 By 16 Bit Complex Multiplier DS3858 - 3.0 June 2000 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s PDF

    parallel Multiplier Accumulator based on Radix-2

    Abstract: DS3707 PDSP16116 PDSP16116A PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter
    Text: PDSP16116 16 X 16 Bit Complex Multiplier Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications.


    Original     		PDSP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit parallel Multiplier Accumulator based on Radix-2 PDSP16318A subtractor using TTL CMOS GG144 4 bit binary full adder and subtractor 32-bit adder block diagram for barrel shifter PDF

    ALU of 4 bit adder and subtractor

    Abstract: MIL-883 PDSP16116 PDSP16116A PDSP16318 logic diagram to setup adder and subtractor using
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s ALU of 4 bit adder and subtractor MIL-883 PDSP16318 logic diagram to setup adder and subtractor using PDF

    BUTTERFLY DSP

    Abstract: WI13 IC5-H10 dar5 AN59 PDSP1601 PDSP16116 PDSP16116A PDSP16318 BR13
    Text: AN59 A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A has been designed with an integral Block Floating Point system which can be used, in conjunction with other Zarlink Semiconductor PDSP parts, to process FFTs with a combination of speed and accuracy previously unobtainable. All the


    Original     		PDSP16116A 20MHz 259us 118us BUTTERFLY DSP WI13 IC5-H10 dar5 AN59 PDSP1601 PDSP16116 PDSP16318 BR13 PDF

    Untitled

    Abstract: No abstract text available
    Text: PDSP16116/A OCTOBER 1996 DS3707 - 4.2 PDSP16116/A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version October 1995 verison, DS3707 - 3.0 The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    Original     		PDSP16116/A DS3707 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDF

    32 bit adder

    Abstract: PDSP16116 MIL-883 PDSP16116A PDSP16318
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s 32 bit adder MIL-883 PDSP16318 PDF

    YR13

    Abstract: PDSP16116
    Text: PDSP16116 16 X 16 Bit Complex Multiplier DS3707 The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex 16116


    Original     		PDSP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit YR13 PDF

    4 bit barrel shifter circuit for left shift

    Abstract: No abstract text available
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s 4 bit barrel shifter circuit for left shift PDF

    block diagram of 32 bit array multiplier

    Abstract: sonar block diagram 32 bit adder block diagram of 16 bit array multiplier 32-bit adder 16 point FFT butterfly 144 pin pga "multiplier accumulator" sonar radar block diagram
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 By 16 Bit Complex Multiplier DS3858 - 3.0 June 2000 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s block diagram of 32 bit array multiplier sonar block diagram 32 bit adder block diagram of 16 bit array multiplier 32-bit adder 16 point FFT butterfly 144 pin pga "multiplier accumulator" sonar radar block diagram PDF

    144 pin pga

    Abstract: PDSP16116 PDSP16116A PDSP16318 diode b10
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 By 16 Bit Complex Multiplier Supersedes July 1993 version, DS3858 - 1.0 DS3858 - 2.0 October 1998 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 144 pin pga PDSP16318 diode b10 PDF

    Untitled

    Abstract: No abstract text available
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s PDF

    logic diagram to setup adder and subtractor

    Abstract: YR10 FFT 1024 point implementing ALU with adder/subtractor PR11 MIL-883 PDSP16116 PDSP16116A PDSP16318 tag l9 230
    Text: PDSP16116/A/MC PDSP16116/A/MC 16 by 16 Bit Complex Multiplier DS3858 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement.


    Original     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 PDSP16318s logic diagram to setup adder and subtractor YR10 FFT 1024 point implementing ALU with adder/subtractor PR11 MIL-883 PDSP16318 tag l9 230 PDF

    Untitled

    Abstract: No abstract text available
    Text: Si GEC P L E S S E Y OCTOBER 1997 S E M I C O N D U C T O R S DS3707 - 5.3 P D S P 16 116 16X16 BIT COMPLEX MULTIPLIER Supersedes October 1996 version, DS3707 - 4.2 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­


    OCR Scan     		DS3707 16X16 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit PDF

    DS3707

    Abstract: No abstract text available
    Text: M ITEL PD SP16116 16 X 16 Bit Complex Multiplier SE M IC O N D U C T O R Supersedes October 1996 version, DS3707 - 4.2 DS3707 - 5.3 October 1997 The PDSP16116 contains four 1 6 x1 6 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup­


    OCR Scan     		SP16116 DS3707 PDSP16116 32-bit PDSP16116A PDSP16318A, 20MHz 20-bit PDF

    Untitled

    Abstract: No abstract text available
    Text: • 1P 1LE S S E Y S E M IC O N D U C T O R S PDSP16112/PDSP16112A 16 x 12 BIT COMPLEX MULTIPLIER • 20M H z C om plex N um ber 16 + 16 x (12 + 12) Multiplication I Pipelined A rchitecture ■ Power Dissipation only 500m W B TT L C om patible Inputs APPLICATIONS


    OCR Scan     		PDSP16112/PDSP16112A PDSP16112/P SP16112A) PDSP16112) 1000mW SP16112A IL-883C PDF

    xlxx

    Abstract: xi12 YI11 yr03
    Text: P LESSEY SEMICONDUCTORS 13E D • 725 1513 OOlOObb 3 PLESSEY W Semiconductors ■ PDSP16112/PDSP16112A 16 x 12 BIT COMPLEX MULTIPLIER (SU P ER SED ES MARCH 1987 EDITION The PDSP16112/PDSP16112A w ill m ultiply a com plex (16 + 16) bit data word by a com plex (12 + 12) bit coefficient


    OCR Scan     		PDSP16112/PDSP16112A PDSP16112/PDSP16112A 20MHz PDSP16112A) 10MHz PDSP16112) 20MHz AC120 7220S13 T-90-20 xlxx xi12 YI11 yr03 PDF

    barrel shifter block diagram

    Abstract: parallel Multiplier Accumulator based on Radix-2 ALU of 4 bit adder and subtractor CD11N TTL ALU of 4 bit adder and subtractor radix-2 YIO 98 PDSP16116 PDSP16116A PDSP16318
    Text: PDSP16116/A/MC MITEL 16 By 16 Bit Complex Multiplier SEM ICON D UCTOR Supersedes July 1993 version, DS3858 - 1.0 DS3858 - 2.0 O ctober 1998 The PDSP16116A will multiply two complex 16 + 16 bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The


    OCR Scan     		PDSP16116/A/MC DS3858 PDSP16116A PDSP16116/A PDSP16318, 10MHz PDSP16116 barrel shifter block diagram parallel Multiplier Accumulator based on Radix-2 ALU of 4 bit adder and subtractor CD11N TTL ALU of 4 bit adder and subtractor radix-2 YIO 98 PDSP16318 PDF

    bfp mark diode

    Abstract: 32-bit adder PS2187 PDSP16330 plessey logic diagram to setup adder and subtractor using PDSP16116 IC to design 2 by 2 binary multiplier PDSP1601 PDSP16318 YR13
    Text: APR IL 1989 < Ä j P L E S S E Y Sem iconductors. P D S P 1 6 1 1 6 16 BY 16 BIT COMPLEX MULTIPLIER SUPERSEDES EDITION IN JU L Y 1988 DSP 1C HANDBOOK The PDSP16116 will multiply two complex (16+16) bit words every 100ns and can be configured to output the


    OCR Scan     		PDSP16116 PDSP16116 100ns 16x16 PDSP16318, 10MHz PDSP16318 bfp mark diode 32-bit adder PS2187 PDSP16330 plessey logic diagram to setup adder and subtractor using IC to design 2 by 2 binary multiplier PDSP1601 YR13 PDF

    aeg diode Si 11 n

    Abstract: No abstract text available
    Text: Si GEC P L E S S E Y S f M I C. O IN D ADVANCE INFORMATION L C T O R S P D S P 1 6 1 1 6 /A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes version in December 1993 Digital Video & Digital Signal Processing 1C Handbook, HB3923-1) The PDSP16116A will m ultiply tw o complex (16 + 1 6 ) bit


    OCR Scan     		HB3923-1) PDSP16116A PDSP16116/A PDSP16116C0 PDSP16116B0 PDSP16116 PDSP16116MCGGDR PDSP16116AC0 aeg diode Si 11 n PDF

    ALU of 4 bit adder and subtractor

    Abstract: 4 bit binary full adder and subtractor PDSP16116 4 bit barrel shifter circuit for left shift radix-2 PDSP16116A PDSP16256 PDSP16318A PDSP16350 PDSP16510
    Text: L L iS S S U b J SEM ICO N DU CTO RS P D S P 1 6 1 1 6 / A 16 BY 16 BIT COMPLEX MULTIPLIER SUPERSEDES JAN UAR Y 1990 EDITION The PDSP16116A will multiply two complex (16+16) bit words every 50ns and can be configured to output the com­ plete complex (32+32) bit result within a single cycle. The data


    OCR Scan     		PDSP16116 PDSP16116A PDSP16116/A 16x16 PDSP16318A, 20MHz PDSP16318As PDSP1601As ALU of 4 bit adder and subtractor 4 bit binary full adder and subtractor 4 bit barrel shifter circuit for left shift radix-2 PDSP16256 PDSP16318A PDSP16350 PDSP16510 PDF

    18 x 16 barrel shifter

    Abstract: No abstract text available
    Text: I ' Si / t o / / GEC P L E S S E Y ADVANCE INFORMATION OSUar-2? W O <1 Q. PDSP16116/A 16 BV16 BIT COMPLEX MULTIPLIER Supersedes version in December 1993 Digital Video & Digital Sfenai Processing 1CHandbook, HB3923-tj The PDSP16116A will muHjalytwo complex (16+15 bit


    OCR Scan     		PDSP16116/A HB3923-tj PDSP16116A 321b4iMultwiiWna8iftgl6cyc PDSPlS1l6/Aecnlainttotir16x16AmyUi P0SP16318, PDSP161 10MHz PDSP-6116MCGQDR 6116ACO 18 x 16 barrel shifter PDF

    4 bit binary multiplier

    Abstract: No abstract text available
    Text: i i s s Q u in S E M IC O N D U C T O R S PDSP 1 6 1 1 6 / A 16 BY 16 BIT COMPLEX MULTIPLIER SUPERSEDES JANUARY 1990 EDITION The PDSP16116A will multiply two complex (16+16) bit words every 50ns and can be configured to output the com­ plete complex (32+32) bit result within a single cycle. The data


    OCR Scan     		PDSP16116A PDSP16 16x16 6318A 20MHz PDSP16116 10MHz 4 bit binary multiplier PDF

    Untitled

    Abstract: No abstract text available
    Text: JANUARY 1990 PILE SSEY S E M IC O N D U C T O R S : P D S P 1 6 1 1 6 / 1 6 1 1 6 A 16 BY 16 BIT COMPLEX MULTIPLIER Supersedes April 1989 Edition The PDSP16116A will multiply two complex (16+16) bit words every 50ns and can be configured to output the com­


    OCR Scan     		PDSP16116A PDSP16116/A 16x16 PDSP16318A, 20MHz PDF