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    Microchip Technology Inc RTSX32SU-CQ208PROTO

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    Microchip Technology Inc RTSX72SU-1CQ256EV

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    RTSX Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    rt54sx32su

    Abstract: RTSX72 RTSX32SU RTSX72-S
    Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 rt54sx32su RTSX72 RTSX32SU RTSX72-S PDF

    Untitled

    Abstract: No abstract text available
    Text: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 PDF

    RTSX32su

    Abstract: Actel a54sx72a tid Silicon Sculptor II
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32su Actel a54sx72a tid Silicon Sculptor II PDF

    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.6 RTSX-S RadTolerant FPGAs for Space Application S p ec i a l F e a tu r es fo r S p ac e • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		TM1019 HiRel a54sx72a unused PDF

    RTSX32su

    Abstract: RTSX32SU CQ84 RTSX72SU
    Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32su RTSX32SU CQ84 RTSX72SU PDF

    RT54SX72SCQ208

    Abstract: CQ208 AC195 SY-PQ208-2 A54SX72A-PQ208 ACTEL CCGA to FBGA Adapter RT54SX32SCQ208 RT54SX32S-CQ208 FG484 A54SX32APQ
    Text: Application Note AC195 Prototyping for the RTSX-S Enhanced Aerospace FPGA Introduction Actel provides radiation-tolerant FPGAs for space applications. However, since the enhanced environmental properties of radiation tolerant devices are not required during prototyping, inexpensive


    Original     		AC195 RT54SX72SCQ208 CQ208 AC195 SY-PQ208-2 A54SX72A-PQ208 ACTEL CCGA to FBGA Adapter RT54SX32SCQ208 RT54SX32S-CQ208 FG484 A54SX32APQ PDF

    RTSX32SU

    Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
    Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32SU RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208 PDF

    RTSX72

    Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
    Text: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX72 RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto PDF

    RTSX32SU

    Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
    Text: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 MIL-ST00 RTSX32SU RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624 PDF

    AF-2-A

    Abstract: A54SX08A A54SX16A A54SX32A A54SX72A AC200 RT54SX72S RT54SX-S hyperlynx
    Text: Application Note AC200 Actel eX, SX-A, and RTSX-S I/Os Introduction The eX, SX-A, and RTSX-S devices have a variety of advanced I/O features, such as PCI compliance, programmable input threshold voltage, configurable output slew rate, and selectable output state during


    Original     		AC200 AF-2-A A54SX08A A54SX16A A54SX32A A54SX72A AC200 RT54SX72S RT54SX-S hyperlynx PDF

    RTSX32SU

    Abstract: RTSX72SU AC251 RT54SX72S RT54SX-S in-rush RTSXSU ACTEL
    Text: Application Note AC251 Power Cycling of RTSX-S Devices Introduction Power cycling may be defined in various terms, based on different applications. In this application note, power cycling refers to consecutive power-up/down sequences of array and I/O voltage supplies of RTSX-S


    Original     		AC251 RTSX32SU RTSX72SU AC251 RT54SX72S RT54SX-S in-rush RTSXSU ACTEL PDF

    RTSX32SU CQ84 PROTO

    Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
    Text: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32SU CQ84 PROTO RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion PDF

    SU 177

    Abstract: RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256
    Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 SU 177 RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256 PDF

    Untitled

    Abstract: No abstract text available
    Text: Application Note Actel eX, SX-A and RTSX-S I/Os I n tro du ct i on V The eX, SX-A and RTSX-S devices have a variety of advanced I/O features, which are not available in other Actel devices, such as PCI compliance, slew-rate control and pull-up/pull-down resistor. Furthermore, these devices are


    Original     		com/apps/guru/feb00/jy1316 PDF

    RT54SX72SCQ208

    Abstract: Actel a54sx72a tid RT54SX72S matsua fuse resistor PQFP die size actel 1020 datasheet ACTEL CCGA 624 mechanical antifuse A54SX72A CC256
    Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RT54SX72SCQ208 Actel a54sx72a tid RT54SX72S matsua fuse resistor PQFP die size actel 1020 datasheet ACTEL CCGA 624 mechanical antifuse A54SX72A CC256 PDF

    ACTEL CCGA 624 mechanical

    Abstract: No abstract text available
    Text: v2 . 0 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 ACTEL CCGA 624 mechanical PDF

    SMD ARAY

    Abstract: No abstract text available
    Text: Revision 6 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 MIL-STD-883B SMD ARAY PDF

    74HC14 oscillator application note

    Abstract: ttl buffer 74hc245 Buffer 74HC245 74HC14 application note 74HC245 application 74HC14 74HC240 74HC245 AC161 TTL Schmitt-Trigger Inverters
    Text: Application Note AC161 Using Schmitt Triggers for Low Slew-Rate Input In t ro d u ct i o n Actel's SX-A and RTSX-S device families are designed to accommodate a variety of I/O standards. This allows users to easily integrate these FPGAs with other devices that have


    Original     		AC161 74HC14 oscillator application note ttl buffer 74hc245 Buffer 74HC245 74HC14 application note 74HC245 application 74HC14 74HC240 74HC245 AC161 TTL Schmitt-Trigger Inverters PDF

    AX2000-CQ256

    Abstract: No abstract text available
    Text: Power Matters. Spaceflight FPGAs RTAX -S/SL RTAX-DSP RT-ProASIC 3 RTSX-SU The leader in programmable digital logic integration for spaceflight applications. Taking Designs from Earth to Outer Space Whether you’re designing for low earth orbit, deep space, or anything in between, Microsemi’s high reliability, low


    Original     		MS2-003-12 AX2000-CQ256 PDF

    HiRel a54sx72a unused

    Abstract: No abstract text available
    Text: Advanced v1.5 RTSX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10


    Original     		TM1019 HiRel a54sx72a unused PDF

    ACTEL CCGA 624 mechanical

    Abstract: 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472
    Text: v2 . 2 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 ACTEL CCGA 624 mechanical 208-Pin CQFP Actel a54sx72a tid CCGA -CG 472 PDF

    RTSX32SU CQ84

    Abstract: Silicon Sculptor II RTSX32SU actel 1020
    Text: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32SU CQ84 Silicon Sculptor II RTSX32SU actel 1020 PDF

    A500K050

    Abstract: No abstract text available
    Text: CorePCI v5.3 Key Features PCI Specification 2.2 Compliant Zero Wait-State Burst Mode Transfers Supports Actel SX, SX-A, RTSX, ProASIC and ProASICPLUS Families Silicon-Proven 33 or 66 MHz Performance1 32-bit or 64-bit PCI Bus Memory, I/O and Configuration Command Support


    Original     		32-bit 64-bit A500K050 PDF

    RTSX32SU

    Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		TM1019 RTSX32SU RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213 PDF