74lv74a
Abstract: LV74A A115-A C101 SN54LV74A SN74LV74A SN74LV74AD
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381F – AUGUST 1997 – REVISED JANUARY 2001 D D D D SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)
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SN54LV74A,
SN74LV74A
SCLS381F
SN54LV74A
000-V
A114-A)
A115-A)
74lv74a
LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74AD
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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SN54LV74,
SN74LV74
SCLS189C
MIL-STD-883C,
JESD-17
300-mil
SN54LV74
SN74LV74
SCBA004C
SDYA010
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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SN54LV74A,
SN74LV74A
SCLS381L
SN54LV74A
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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SN54LV74A,
SN74LV74A
SCLS381L
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE
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SN54LV74A,
SN74LV74A
SCLS381I
000-V
A114-A)
A115-A)
SN54LV74A
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74, SN74LV74 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS189C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV74,
SN74LV74
SCLS189C
MIL-STD-883C,
JESD-17
300-mil
SN54LV74
SN74LV74
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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SN54LV74A,
SN74LV74A
SCLS381L
000-V
A114-A)
A115-A)
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 2525Q
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE
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SN54LV74A,
SN74LV74A
SCLS381I
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
2525Q
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381I – AUGUST 1997 – REVISED OCTOBER 2002 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE
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Original
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SN54LV74A,
SN74LV74A
SCLS381I
000-V
A114-A)
A115-A)
SN54LV74A
SN74LV74APWR
SN74LV74ARGYR
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR LV74a
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381J – AUGUST 1997 – REVISED AUGUST 2003 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE
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SN54LV74A,
SN74LV74A
SCLS381J
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
LV74a
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR 74LV74
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
74LV74
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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SN54LV74A,
SN74LV74A
SCLS381L
000-V
A114-A)
A115-A)
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
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PDF
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A115-A
Abstract: C101 SN54LV74A SN74LV74A SN74LV74ARGYR
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
SN54LV74A
A115-A
C101
SN54LV74A
SN74LV74A
SN74LV74ARGYR
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PDF
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74LV74
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
000-V
A114-A)
A115-A)
10Timers
74LV74
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PDF
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SN54LV74A
Abstract: SN74LV74A 122d
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381E – AUGUST 1997 – REVISED MAY 2000 D D D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV74A,
SN74LV74A
SCLS381E
MIL-STD-883,
SN54LV74A
SN74LV74A
122d
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
000-V
A114-A)
A115-A)
10line
SN74LV74A
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV74,
SN74LV74
SCLS189C
MIL-STD-883C,
JESD-17
300-mil
SN54LV74
SN74LV74
SDYA010
SDYA012
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381J – AUGUST 1997 – REVISED AUGUST 2003 SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE
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Original
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SN54LV74A,
SN74LV74A
SCLS381J
000-V
A114-A)
A115-A)
SN54LV74A
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PDF
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SN54LV74
Abstract: SN74LV74
Text: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
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Original
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SN54LV74,
SN74LV74
SCLS189C
MIL-STD-883C,
JESD-17
300-mil
SN54LV74
SN74LV74
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PDF
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74LV74
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381L − AUGUST 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381L
000-V
A114-A)
A115-A)
74LV74
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PDF
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SN54LV74A
Abstract: SN74LV74A SN74LV74ARGYR A115-A C101
Text: SN54LV74A, SN74LV74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS SCLS381K − AUGUST 1997 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP Output Ground Bounce SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS,
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Original
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SN54LV74A,
SN74LV74A
SCLS381K
SN54LV74A
SN54LV74A
SN74LV74A
SN74LV74ARGYR
A115-A
C101
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74, SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SC LS 189C - FEBRUARY 1993 - REVISED APRIL 1986 EPIC Enhanced-Performance Implanted CMOS 2-|i Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc. Ta = 25°C Typical V q h v (Output Voh Undershoot)
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OCR Scan
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SN54LV74,
SN74LV74
MIL-STD-883C,
JESD-17
300-mll
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PDF
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Untitled
Abstract: No abstract text available
Text: SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381 A -A U G U S T 1997-R E V IS E D OCTOBER 1997 EPIC Enhanced-Performance Implanted CMOS Process SN54LV74A . . J OR W PACKAGE SN74LV74A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW)
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OCR Scan
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SN54LV74A,
SN74LV74A
SCLS381
1997-R
JESD17
MIL-STD-883,
300-mil
SN54LV74A
SN74LV74A
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PDF
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